Pipeline Hazards - Types with Examples (7M)

1. Pipeline Concept
Pipelining overlaps fetch-decode-execute stages of multiple instructions. Ideal speedup = n stages. But dependencies cause hazards → pipeline stalls (bubbles) or flushes, reducing throughput. Clock must also handle slowest stage + latch delay.

2. What is Hazard?
Situation where next instruction cannot execute in its designated clock cycle due to resource / data / control dependency.

3. Three Types (Stallings Classification):

A) Structural Hazard - Resource Conflict

Occurs when hardware resources insufficient to support overlapping execution.

Example: Single memory for instruction + data (Von Neumann). IF stage needs memory to fetch, MEM stage needs memory for load/store at same cycle.

Cycle: 1   2   3   4   5
I1:    IF  ID  EX  MEM WB
I2:         IF  ID  EX  MEM*  <- MEM conflict with I1 MEM
I3:              IF*  ID ...  * structural stall 1 cycle

Solutions: Harvard architecture (separate I-cache/D-cache), separate Instruction & Data memories, multi-port register file, pipelined ALU.

Other example: Single ALU for EX and address calculation.

B) Data Hazard - Data Dependency

Instruction needs data still being computed/ not yet written back.

Classification per register access:

1. RAW (Read After Write) - True dependency - Most common

I1: ADD R1, R2, R3   ; R1 = R2+R3
I2: SUB R4, R1, R5   ; needs R1 -> must wait for WB of I1

If pipelined without forwarding, I2 reads stale R1. With 5-stage pipeline, need 2 stalls or forwarding.

2. WAR (Write After Read) - Anti-dependency (only in out-of-order)

I1: ADD R2, R1, R3   ; reads R1
I2: SUB R1, R4, R5   ; writes R1 - must not overwrite before I1 reads

3. WAW (Write After Write) - Output dependency

I1: ADD R1, R2, R3
I2: SUB R1, R4, R5   ; both write R1 -> order matters

Sub-types by pipeline stage:

• Load-Use Hazard: Load followed by use needs 1 stall even with forwarding.

LW  R1, 0(R2)
ADD R3, R1, R4  ; needs R1 from MEM stage - 1 bubble inserted

• EX-Use Hazard: ALU result forwarded from EX/MEM latch.

Example Timing with Forwarding vs Stall:

Without forwarding:
ADD R1,R2,R3
SUB R4,R1,R5  -> stall 2 cycles

With forwarding (bypass EX->EX):
ADD: IF ID EX MEM WB
SUB:    IF ID --EX-- MEM WB  (forwarded path from EX/MEM to ALU input)

Solutions: Data Forwarding/Bypassing, Register Scoreboarding, Tomasulo, Compiler scheduling (insert NOP), stalls/bubbles.

C) Control Hazard - Branch / Jump Hazard

Due to branches, next PC unknown until decode/execute.

BEQ R1, R2, LABEL  ; branch taken ?
Next instr fetch is speculative -> if taken, fetched instr wrong -> flush

Cycle 1: IF BEQ
Cycle 2: IF next (wrong) | ID BEQ -> branch decoded
Cycle 3: IF next2 | ID next | EX BEQ -> target known -> flush IF,ID

Penalty = 2-3 cycles in simple 5-stage (branch resolved in EX). Modern pipelines predict.

Example: JMP Label, CALL, interrupts.

Solutions:

1. Stall until target known (simple)
2. Branch Prediction - Static (predict not taken) / Dynamic (1-bit, 2-bit saturating counter, BTB)
3. Branch Target Buffer (BTB) + Branch History Table
4. Delayed Branch - Fill delay slot with useful instruction (MIPS)
5. Speculative execution + flush on mispredict
6. Loop unrolling

4. Summary Table

Hazard	Cause	Example	Stall Cycles	Fix
Structural	Lack of HW	One memory	1	Add HW, split cache
RAW Data	Need result	ADD->SUB R1	1-2 (0 with fwd)	Forwarding, NOP
WAR/WAW	Write conflict	Out-of-order only	0 in-order	Renaming
Control	Branch PC unknown	BEQ, JMP	2-3	Predict, BTB, delay slot

5. Performance Impact

Hazard stalls increase CPI:
CPI_pipelined = 1 + stall_cycles_per_instr
Speedup = n / (1 + stalls) * (cycle_unpipelined / cycle_pipelined)

Goal of hazard handling is to keep CPI ~1.

Diagram to draw in exam: 5-stage pipeline (IF-ID-EX-MEM-WB) reservation table showing overlapping and bubble insertion for each hazard type.