Solution - Pipeline Hazards and Types

Pipeline Hazard: A situation that prevents the next instruction in the pipeline from executing during its designated clock cycle. It causes stalls/bubbles, reduces speedup and throughput, breaking ideal pipeline flow.

Three Major Types:

1. Structural Hazards (Resource Conflict):
Occurs when hardware resources required by two or more instructions overlap in same clock cycle.

• Cause: Insufficient hardware duplication. E.g., single memory for both instruction fetch and data access (von Neumann), single ALU, single register file write port.
• Example: In 4-stage pipeline IF-ID-EX-MEM, if instruction I1 is in MEM accessing memory and I4 needs IF at same time with single memory port - conflict.
• Solution: Separate instruction and data memories (Harvard), duplicate resources, pipeline register file, stall pipeline (bubble).

2. Data Hazards (Data Dependency):
Occurs when instructions exhibit data dependency and pipeline changes order of read/write accesses.
There are three types:

• RAW (Read After Write) - True Dependency: $I_2$ tries to read operand before $I_1$ writes it.
  ADD R1,R2,R3 ; SUB R4,R1,R5 -> SUB needs R1 before ADD writes. Most common. Causes stalls.
• WAR (Write After Read) - Anti-dependency: $I_2$ writes before $I_1$ reads. Occurs in out-of-order execution.
  ADD R1,R2,R3 ; MUL R2,R4,R5 -> MUL writes R2 before ADD reads it.
• WAW (Write After Write) - Output dependency: Both write same register out-of-order.
  ADD R1,R2,R3 ; MUL R1,R4,R5 -> ordering of writes matters.
• Solutions: Data forwarding/bypassing, operand forwarding, compiler reordering, pipeline interlocks, register renaming, stalling.

3. Control Hazards (Branch Hazards):
Occurs due to branch instructions (conditional/unconditional) - pipeline doesn't know next PC until branch is resolved.

• Example: BEQ R1,R2,target - whether to fetch next sequential instruction or target is unknown until EX/MEM stage. Fetching wrong instruction causes flush.
• Penalty: If pipeline has 5 stages and branch resolved at stage 3, 2 instructions already fetched must be flushed if branch taken.
• Solutions:
  • Stall/Flush: freeze pipeline until branch resolved (simple but slow).
  • Branch Prediction: static (predict not-taken) or dynamic (2-bit predictor, BTB).
  • Delayed Branch: compiler fills delay slot with useful independent instruction after branch.
  • Branch Target Buffer (BTB) and Prefetch.

Additional: Some textbooks add Pipeline Data Hazards sub-class and mention handling via scoreboarding/Tomasulo.

Hazards reduce ideal CPI=1 to CPI >1; effective speedup $< k$.