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COMPUTER ORGANIZATION & ARCHITECTUREThe stage delays in a four-stage pipeline are 800, 500, 400 and 300 picoseconds. The first stage (with delay 800 picoseconds) is replaced with a functionally equivalent design involving two stages with respective delays 600 and 350 picoseconds. What would be the throughput increase (in percentage) of the pipeline?20237mCOMPUTER ORGANIZATION & ARCHITECTUREA non-pipelined processor has a clock rate of 2.5 GHz and an average CPI (cycles per instruction) of 4. An upgrade to the processor introduces a five-stage pipeline. However, due to internal pipeline delays, such as latch delay, the clock rate of the new processor has to be reduced to 2 GHz. (a) What is the speedup achieved for a typical program? (b) What is the MIPS rate for each processor?202214mCOMPUTER ORGANIZATION & ARCHITECTUREExplain two techniques for enhancing the performance of computers with multiple execution pipelines.20227mCOMPUTER ORGANIZATION & ARCHITECTUREThe performance of a pipelined processor suffers if (i) The pipeline stages have different delays (ii) Consecutive instruction are dependent on each other (iii) The pipeline stages share hardware resources (iv) All of these20232m
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