(a) Speedup

Let $N$ = no. of instructions.

Non-pipelined:

• Clock $f_{np}=2.5\text{ GHz} \Rightarrow T_{np}=0.4\text{ ns}$
• $CPI_{np}=4$
• $T_{old}= N\cdot CPI_{np}\cdot T_{np}= N\cdot 4 / f_{np}= N\cdot 1.6\text{ ns}$

Time per instruction $= 1.6\text{ ns}$.

Pipelined (5-stage, ideal, no hazards):

• $f_{p}=2.0\text{ GHz} \Rightarrow T_{p}=0.5\text{ ns}$
• Ideal $CPI_{p}=1$ (one instruction completes per cycle in steady state). Ignoring fill/drain overhead for large $N$: $T_{new}= N\cdot 1 \cdot T_{p}= N\cdot 0.5\text{ ns}$.

With fill overhead: $T_{new}= (k+N-1)T_{p}$ where $k=5$, $\approx N T_{p}$ for $N\gg k$.

$$Speedup = \frac{T_{old}}{T_{new}} = \frac{CPI_{np}/f_{np}}{CPI_{p}/f_{p}} = \frac{4/2.5}{1/2}= \frac{1.6}{0.5}=3.2$$

So $\approx 3.2\times$ speedup in the ideal hazard-free case. If pipeline stalls/hazards raise $CPI_{p}$ to e.g. 1.2 then $Speedup = (4/2.5)/(1.2/2)=2.67$.

Maximum theoretical speedup ignoring clock reduction: $CPI_{np}/CPI_{p}=4$; with clock penalty $2/2.5=0.8$, net $4\times0.8=3.2$.

(b) MIPS rate

$$MIPS = \frac{f}{CPI\times10^{6}}$$

• Non-pipelined: $MIPS_{np}= \dfrac{2.5\times10^{9}}{4\times10^{6}} = \mathbf{625\ MIPS}$

• Pipelined (ideal $CPI=1$): $MIPS_{p}= \dfrac{2.0\times10^{9}}{1\times10^{6}} = \mathbf{2000\ MIPS}$

If hazards included, e.g. $CPI_{p}=1.14$, $MIPS_{p}\approx 1754$. In general $MIPS_{p}=2000/CPI_{p}$.

Throughput gain $=2000/625=3.2$ same as speedup.