A non-pipelined processor has a clock rate of 2.5 GHz and an average C

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Module 3: Pipelining

202214m

A non-pipelined processor has a clock rate of $2.5$ GHz and an average CPI (cycles per instruction) of $4$ . An upgrade to the processor introduces a five-stage pipeline. However, due to internal pipeline delays, such as latch delay, the clock rate of the new processor has to be reduced to $2$ GHz.

(a) What is the speedup achieved for a typical program?

(b) What is the MIPS rate for each processor?

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