RISC instruction set keeps only load/store accessing memory to simplify pipeline. Yet stack frames, parameter passing and spills cause many register↔memory moves. Two approaches to minimize:

1. Hardware Approach - Large Register File with Register Windows (Berkeley RISC I)

Provide very large register file (e.g., 32-128 registers) and partition into overlapping windows per procedure.

• Registers divided into: Global (G0-Gn) - shared by all procedures, Local, In, Out.
• On call, CPU switches to new window: Out registers of caller become In registers of callee (overlap) - parameters passed without memory store/load.
• Only window pointer changes, no memory traffic for save/restore on call/return unless window overflows/underflows.
• Example: RISC I has 8 windows ×16 registers + 10 globals = 138 registers, but only 32 visible at a time. Sun SPARC implements this.
• Effectively caches procedure context in registers, cutting memory operations by 50%+.

Alternative hardware: Register Stack with renaming.

2. Software/Compiler Approach - Optimized Register Allocation

• Efficient graph-coloring register allocator keeps most-used variables (loop indices, temporaries) in registers for entire lifetime, minimizing loads/stores.
• Compiler optimizations: keep variables in registers across basic blocks, common subexpression elimination, loop invariant movement, leaf-procedure optimization.
• Instruction scheduling and delayed load handling: compiler inserts independent instructions after load to avoid stall, reducing load interlocks.
• Stanford MIPS approach: Use compiler rather than hardware windows - relies on large but flat register file (32 registers) and smart allocation.

Both aim to exploit locality: hardware caches context via windows; software keeps working set in registers. Combined, RISC achieves CPI ≈1 while CISC spends many cycles on register-memory traffic.