Addressing Mode - Why Techniques & Two Modes Without Address Field (7M)

A) What is Addressing Mode?

Field A in instruction format OPCODE | A is not necessarily the operand itself. Addressing mode is the rule CPU uses to interpret A to locate the operand or Effective Address (EA). Decoder uses mode bits (ModR/M in x86) to compute EA = f(A, Registers, PC, Indirect chain).

Without modes, every instruction would need full absolute address → large code, inflexible.

Example formats:

Format: | Opcode | Mode | Address field A |  (16-32 bit system)
EA derivation depends on Mode:
 Mode 00: EA = A           (Direct)
 Mode 01: EA = (A)         (Indirect)
 Mode 10: Operand = A      (Immediate)

B) Why Do Computers Use Addressing Mode Techniques?

1. Flexibility to High-Level Constructs:

   • Arrays: Base + Index*Scale access A[i] without computing address manually each time.
   • Pointers/Dynamic structures: Indirect Mov R,(P) dereferences pointer.
   • Records/Structs: Displacement Struct + Offset.
   • Position-Independent Code: Relative PC + Disp for branching/ PIC.

2. Reduce Instruction Size / Code Density:

   • Immediate 8-bit vs 32-bit address, Register mode uses 3 bits to select register vs 32-bit absolute. Keeps program shorter → fewer instruction fetches.

3. Support Multiple Data Structures with Few OpCodes:

   • One ADD opcode works for ADD #5, ADD [2000H], ADD [BX+SI] differing only by mode bits, not separate opcode per operand location.

4. Efficient Loop & Stack Handling:

   • Auto-increment/decrement (R)+ , -(R) for traversing arrays/stacks without extra INC instruction; Stack mode implied via SP.

5. Virtual Memory & Protection (x86):

   • Segmentation + indexed modes hide physical address calculation.

6. Performance: Register mode fastest (no memory access); with modes, compiler can keep hot variables in registers, use immediate for constants (no memory load). Reduces memory traffic.

In summary: Modes bridge gap between programmer's abstract view (variables, pointers, arrays, constants) and hardware's physical view (linear memory addresses) while minimizing instruction bits.

C) Two Modes That Do NOT Use Address Field

Some instructions have no address operand at all; operand location is implied or is the instruction itself.

1. Implied / Implicit / Stack Mode
No address field present; operand(s) implicitly assumed.

• Definition: Opcode itself implies where operand resides - typically top of stack, accumulator, or flags register.
• Operation: EA not needed; CPU internally uses SP or accumulator.

Examples:

• Stack Zero-address: PUSH AX ; POP BX ; ADD (in stack machine) → pops TOS and TOS-1, pushes sum. E.g., PUSH 2; PUSH 3; ADD → stack top = 5.
• Accumulator implied: CMA (Complement Accumulator), INCA (Increment A) - operand is always AC.
• Flag implied: CLC (Clear Carry), STC, CLI/STI - operates on FLAGS, no operand.
• Example encoding: CLC = F8H (8086) - 1 byte, no address bits. PUSH AX = 50H.
• EA calculation: None, SP used: PUSH: SP=SP-2, Mem[SP]=AX. No address in instruction stream.

2. Immediate Mode
Operand value itself IS the address field - no memory/register address is referenced beyond instruction.

• Definition: Operand = A where A is the value encoded in instruction after opcode. No EA computation, no extra memory fetch beyond instruction fetch.
• Distinctness: Technically it has an "address field" but it does not contain an address; it contains data. For exam classification, it counts as no-address-field-needed for operand location (value fetched alongside instruction).

Examples:

• MOV AX, 1234H (8086: B8 34 12) - moves constant 0x1234 to AX. 1234H is part of instruction.
• ADD R1, #10 (Assembly # denotes immediate): R1 = R1 + 10, 10 encoded as 8-bit immediate 00001010.
• CMP AL, 5 Immediate 5 compared to AL.
• Encoding advantage: 2-4 byte instruction vs 6-byte load from memory pool.

Note: Some texts also call Register mode as not using address field (register ID is attribute, not memory address), but exam expects Implied and Immediate as canonical two that use no memory address. Mention Register as alternative if needed.

Contrast:
 Direct:  | LDA | 2000H | -> need to fetch Mem[2000H] (extra cycle)
 Immediate:| MVI | 25H   | -> value 25H used directly, no extra fetch
 Implied: | CLC |       -> no field at all

Tip for diagram: Draw instruction format boxes: Immediate shows Opcode | Immediate Value and Implied shows only Opcode.