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COMPUTER ORGANIZATION & ARCHITECTUREA set-associative cache has a block size of four 16-bit words and a set size of 2. The cache can accommodate a total of 4096 words. The main memory size that is cacheable is 64K 32 bits. Design the cache structure and show how the processor’s addresses are interpreted.20227mMICROPROCESSORSTotal bit addressable area in RAM of 8051 microcontroller is ____? (i) 8 bytes (ii) 4 bytes (iii) 16 bytes (iv) 32 bytes20222mCOMPUTER ORGANIZATION & ARCHITECTUREHow many 128 × 8 RAM chips are needed to provide a memory capacity of 2048 bytes?20162mMICROPROCESSORSWhich type of memory in 8051 is bit-addressable? (i) Entire RAM (ii) Register bank (iii) 16 bytes of internal RAM from 20H to 2FH (iv) Entire ROM20242m
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