A) Virtual address → Physical address mapping (Paging)

Virtual address generated by CPU is not real RAM address. MMU translates via Page Table + TLB.

Assume $V=32$ bits, page $4$ KB $=2^{12}$ B $\Rightarrow$ offset $12$b, VPN $20$b.

VA (32b): [ VPN 20b | Offset 12b ]
                 |
                 v
          +-------------------+
          | TLB (cache)       |---- hit ----> PFN
          | VPN -> PFN        |
          +---------+---------+
                    | miss
                    v
          Page Table in RAM (PTBR points)
          PTE: [ PFN | valid | prot | dirty | ref ]
                    |
                    v
PA (32b): [ PFN 20b | Offset 12b ]  (concatenation)

Steps:

1. Split VA into VPN + offset.
2. Search TLB ( ~64-512 entries, associative). Hit → PFN in 1 cycle.
3. Miss → hardware walks page table (often 2-level: Dir + Page table) in memory; may fault.
4. If PTE valid=1 → $PA = PFN \ll 12 | offset$; check protection.
5. If valid=0 → Page fault → OS loads page from disk to frame, updates PTE, restarts.
6. TLB updated.

Segmentation variant: $VA = segment+offset$ → segment table → page table. But paging alone is core.

---

B) Cache Write Methods

When CPU writes, cache and main memory can become incoherent. Policies:

1. Write-Through

• Write to both cache and main memory simultaneously.
• Simple, coherent, but every write goes to bus → high traffic, slow.
• Usually with write buffer to hide latency.
• On read miss, block fetched.

CPU Write → Cache + Memory (together)

2. Write-Back (Copy-Back)

• Write only to cache; set Dirty bit per block. Memory updated only on eviction of dirty block.
• Reduces bus traffic (many writes coalesced). Faster.
• Needs dirty bit + extra control; memory stale until write-back.

CPU Write → Cache (dirty=1)  ---- later on replace ---> Memory

3. Allocation policy on Write Miss

• Write-Allocate (Fetch on Write): On write miss, load block to cache then write (common with write-back).
• No-Write-Allocate (Write-Around): On write miss, write directly to memory, not loading to cache. Common with write-through to avoid polluting cache with write-only data.

Typical combos:

• Write-Through + No-Write-Allocate
• Write-Back + Write-Allocate (most performant, used in L1/L2)

Comparison:

Property	Write-Through	Write-Back
Memory update	Immediate	Deferred (on evict)
Bus traffic	High	Low
Dirty bit	No	Yes
Speed	Slower	Faster
Coherence	Simple	Complex (need snooping)

Example: $4$-way cache: Write hit in write-back sets dirty; on replacement if dirty=1, 32B block written back to RAM before loading new block.