Types of Instruction Formats

Instruction format defines fields in a machine instruction: opcode, operand addresses, mode. Length and field count trade code density vs decode simplicity.

Let $Op$ = opcode, $A_i$ = address/operand.

1. Zero-Address Format (Stack-organized)

No address field; operands on stack (TOS). Implicit.
$Op$ alone; $T \leftarrow T \circ TOS$; push/pop.
Example: PUSH A; PUSH B; ADD; POP C does $C\leftarrow A+B$.
Need PUSH, POP, ADD, SUB, MUL etc. Zero addresses in arithmetic instr.
e.g. ADD = $TOS\leftarrow TOS + TOS_{-1}$.

Adv: No address bits, short instr. Dis: Stack bottleneck, extra pushes.

2. One-Address Format (Accumulator)

One field: $Op\; A$ where one operand is Accumulator (AC) implicitly.
$AC \leftarrow AC \circ M[A]$
Example: LOAD X ($AC\leftarrow M[X]$), ADD Y ($AC\leftarrow AC+M[Y]$), STORE Z ($M[Z]\leftarrow AC$), MUL X.
Only one memory address per arithmetic instr. Used in Mano Basic Computer.

3. Two-Address Format

Fields: $Op\; A_1\; A_2$ : $A_1 \leftarrow A_1 \circ A_2$
Both operands specified, one also destination. Reduces moves.
Example: MOV R1,R2 ($R1\leftarrow R2$), ADD R1, X ($R1\leftarrow R1+M[X]$), SUB R1,R2 ($R1\leftarrow R1-R2$).
8086 ADD AX,BX is two-address (register-register). Saves fetch vs three-address.

4. Three-Address Format

Fields: $Op\; A_1\; A_2\; A_3$ : $A_1 \leftarrow A_2 \circ A_3$
All operands specified, destination separate. Most expressive, but longest (e.g. 32-bit: 8-bit Op +3x8-bit addr).
Example: ADD R1,R2,R3 ($R1\leftarrow R2+R3$), MUL X,Y,Z ($X\leftarrow Y\times Z$).
Used in RISC (ARM, MIPS uses register variant $R$-type).

5. Other / Variable Formats (per COA syllabus)

• Variable-length: CISC (x86) mixes 1 to 15 bytes; opcode + ModR/M + displacement + immediate. Dense but complex decode.
• Fixed-length: RISC (MIPS 32-bit): $R$ (register), $I$ (immediate), $J$ (jump) formats.
  Example MIPS: R: op(6)|rs(5)|rt(5)|rd(5)|shamt|funct, I: op|rs|rt|imm16, J: op|addr26.

Format	Addresses per instr	Memory refs per operation	Example
3-addr	3	3-4	ADD R1,R2,R3
2-addr	2	2-3	ADD R1,R2
1-addr	1	2	ADD X (AC implicit)
0-addr	0	1 (stack)	ADD

Choice affects instruction length, code size, registers needed, and CPI. Modern designs favor 2/3-address register formats + load/store architecture.