2023 question paper
COMPUTER ORGANIZATION & ARCHITECTURE
29 questions
Q1(a). A pipeline stage (i) Is sequential circuit (ii) Is combination circuit (iii) Consists of both sequential and combinational circuit (iv) None of these20232m
Module 3: Pipelining
View this question on its own page →A pipeline stage
(i) Is sequential circuit
(ii) Is combination circuit
(iii) Consists of both sequential and combinational circuit
(iv) None of theseQ1(b). A direct mapped cache memory with n blocks is nothing but which of the following set associative cache memory originations (i) 0-way set associative (ii) 1-way set associative (iii) 2-way set associative (iv) n-way set associative20232m
Module 4: Memory Organization
View this question on its own page →A direct mapped cache memory with blocks is nothing but which of the following set
associative cache memory originations(i) 0-way set associative
(ii) 1-way set associative
(iii) 2-way set associative
(iv) n-way set associativeQ1(c). The performance of a pipelined processor suffers if (i) The pipeline stages have different delays (ii) Consecutive instruction are dependent on each other (iii) The pipeline stages share hardware resources (iv) All of these20232m
Module 3: Pipelining
View this question on its own page →The performance of a pipelined processor suffers if
(i) The pipeline stages have different delays
(ii) Consecutive instruction are dependent on each other
(iii) The pipeline stages share hardware resources
(iv) All of theseQ1(d). A computer with cache access time of 100\,ns, a main memory access time of 1000\,ns, and a hit ratio of 0.9 produces an average access time of (i) 250\,ns (ii) 200\,ns (iii) 190\,ns (iv) None of these20232m
Module 4: Memory Organization
View this question on its own page →A computer with cache access time of , a main memory access time of , and a hit ratio of produces an average access time of
(i)
(ii)
(iii)
(iv) None of theseQ1(e). Which of the following has no practical usage? (i) SISD (ii) SIMD (iii) MISD (iv) MIMD20232m
Module 3: Pipelining
View this question on its own page →Which of the following has no practical usage?
(i) SISD
(ii) SIMD
(iii) MISD
(iv) MIMDQ1(e). Which of the following has no practical usage? (i) SISD (ii) SIMD (iii) MISD (iv) MIMD20232m
Module 1: Functional Block of computer and Data representaion
View this question on its own page →Which of the following has no practical usage?
(i) SISD
(ii) SIMD
(iii) MISD
(iv) MIMDQ1(f). A micro programmed control unit: (i) Is faster than a hardwired control unit (ii) Facilitates easy implementation of new instructions (iii) Is useful when every small program is to be run (iv) Usually refers to the control unit of the microprocessor20232m
Module 2: x86 Architecture, CPU Control, I/O, Memory System Design
View this question on its own page →A micro programmed control unit:
(i) Is faster than a hardwired control unit
(ii) Facilitates easy implementation of new instructions
(iii) Is useful when every small program is to be run
(iv) Usually refers to the control unit of the microprocessorQ1(g). In memory-mapped I/O: (i) The I/O devices and the memory share the same address space. (ii) The I/O device have a separate address space (iii) The memory and I/O device have an associated address space (iv) A part of the memory is specifically set aside for the I/O operation20232m
Module 2: x86 Architecture, CPU Control, I/O, Memory System Design
View this question on its own page →In memory-mapped I/O:
(i) The I/O devices and the memory share the same address space.
(ii) The I/O device have a separate address space
(iii) The memory and I/O device have an associated address space
(iv) A part of the memory is specifically set aside for the I/O operationQ1(h). How many 128x8 bit RAMs are required to design 32 kx 32 bit RAM? (i) 512 (ii) 128 (iii) 1024 (iv) 3220232m
Module 4: Memory Organization
View this question on its own page →How many 128x8 bit RAMs are required to design 32 kx 32 bit RAM?
(i) 512
(ii) 128
(iii) 1024
(iv) 32Q1(i). The stalling of the processor due to the unavailability of the instruction is called as: (i) Control hazard (ii) Structural hazard (iii) Input hazard (iv) None of the above20232m
Module 3: Pipelining
View this question on its own page →The stalling of the processor due to the unavailability of the instruction is called as:
(i) Control hazard
(ii) Structural hazard
(iii) Input hazard
(iv) None of the aboveQ1(j). The addressing mode, where you directly specify the operand value is: (i) Immediate (ii) Direct (iii) Definite (iv) Relative20232m
Module 2: x86 Architecture, CPU Control, I/O, Memory System Design
View this question on its own page →The addressing mode, where you directly specify the operand value is:
(i) Immediate
(ii) Direct
(iii) Definite
(iv) RelativeQ2(a). What are the hazards in pipeline architecture? Explain its types with suitable example.20237m
Module 3: Pipelining
View this question on its own page →What are the hazards in pipeline architecture? Explain its types with suitable example.
Q2(b). What is addressing mode? Why do computers use addressing mode techniques? Explain two modes with example, which do not use address fields.20237m
Module 1: Functional Block of computer and Data representaion
View this question on its own page →What is addressing mode? Why do computers use addressing mode techniques?
Explain two modes with example, which do not use address fields.Q3(a). A 4-way set associative cache memory unit with a capacity of 16 KB is built using a block size of 8 words. The word length is 32 bits. The size of the physical address space is 4 GB. Find the number of bits for TAG, SET, and WORD fields in the address generated by CPU.20237m
Module 4: Memory Organization
View this question on its own page →A 4-way set associative cache memory unit with a capacity of 16 KB is built using a block size of 8 words. The word length is 32 bits. The size of the physical address space is 4 GB. Find the number of bits for TAG, SET, and WORD fields in the address generated by CPU.
Q3(b). How is the virtual address mapped into physical address? What are the different methods of writing into cache?202314m
Module 4: Memory Organization
View this question on its own page →How is the virtual address mapped into physical address? What are the different methods of writing into cache?
Q4(a). What are the different types of instruction formats?20237m
Module 2: x86 Architecture, CPU Control, I/O, Memory System Design
View this question on its own page →What are the different types of instruction formats?
Q4(b). Discuss the different mapping techniques used in cache memories and their relative merits and demerits.20237m
Module 4: Memory Organization
View this question on its own page →Discuss the different mapping techniques used in cache memories and their relative merits and demerits.
Q5(a). Design a 4-bit carry-look ahead adder and explain its operation with an example.20237m
Module 1: Functional Block of computer and Data representaion
View this question on its own page →Design a 4-bit carry-look ahead adder and explain its operation with an example.
Q5(b). Consider a direct mapped cache with 8 cache blocks (numbered 0-7). If the memory block requests are in the following order 3, 5, 2, 8, 0, 63, 9, 16, 20, 17, 25, 18, 30, 24, 2, 63, 5, 82, 17, 24. What would be the status of cache blocks (block numbers residing in cache) at the end of the sequence.20237m
Module 4: Memory Organization
View this question on its own page →Consider a direct mapped cache with 8 cache blocks (numbered 0-7). If the memory block requests are in the following order 3, 5, 2, 8, 0, 63, 9, 16, 20, 17, 25, 18, 30, 24, 2, 63, 5, 82, 17, 24. What would be the status of cache blocks (block numbers residing in cache) at the end of the sequence.
Q6(a). What is DMA? Describe how DMA is used to transfer data from peripherals.20237m
Module 2: x86 Architecture, CPU Control, I/O, Memory System Design
View this question on its own page →What is DMA? Describe how DMA is used to transfer data from peripherals.
Q6(b). Differentiate between hardwired and micro programmed control unit. Explain each component of hardwired control unit organization.20237m
Module 2: x86 Architecture, CPU Control, I/O, Memory System Design
View this question on its own page →Differentiate between hardwired and micro programmed control unit. Explain each component of hardwired control unit organization.
Q7(a). What do you mean by asynchronous data transfer? Explain strobe control and hand shaking mechanism.20237m
Module 2: x86 Architecture, CPU Control, I/O, Memory System Design
View this question on its own page →What do you mean by asynchronous data transfer? Explain strobe control and hand shaking mechanism.
Q7(b). Show the systematic multiplication process of (20) x (-19) using Booth's algorithm.20237m
Module 1: Functional Block of computer and Data representaion
View this question on its own page →Show the systematic multiplication process of (20) x (-19) using Booth's algorithm.
Q8(a). The stage delays in a four-stage pipeline are 800, 500, 400 and 300 picoseconds. The first stage (with delay 800 picoseconds) is replaced with a functionally equivalent design involving two stages with respective delays 600 and 350 picoseconds. What would be the throughput increase (in percentage) of the pipeline?20237m
Module 3: Pipelining
View this question on its own page →The stage delays in a four-stage pipeline are 800, 500, 400 and 300 picoseconds. The first stage (with delay 800 picoseconds) is replaced with a functionally equivalent design involving two stages with respective delays 600 and 350 picoseconds. What would be the throughput increase (in percentage) of the pipeline?
Q8(b). Explain IEEE standard for floating point representation with example.20237m
Module 1: Functional Block of computer and Data representaion
View this question on its own page →Explain IEEE standard for floating point representation with example.
Q9(a). Write short notes on: Paging20237m
Q9(b). Write short notes on: Memory interleaving20237m
Module 4: Memory Organization
View this question on its own page →Write short notes on: Memory interleaving
Q9(c). Write short notes on: Privileged and non-privileged instructions20237m
Module 2: x86 Architecture, CPU Control, I/O, Memory System Design
View this question on its own page →Write short notes on: Privileged and non-privileged instructions
Q9(d). Write short notes on: Locality of reference20237m
Module 4: Memory Organization
View this question on its own page →Write short notes on: Locality of reference