DMA - Direct Memory Access

1. What is DMA?

DMA is an I/O technique where data is transferred directly between memory and peripheral (I/O device) without continuous CPU intervention. A dedicated hardware controller - DMAC (DMA Controller) - takes control of the system buses (steals cycles) and performs the transfer at memory speed.

Without DMA, CPU does programmed I/O (polling/interrupt) moving each byte/word via IN/OUT instructions - slow and wastes CPU cycles.

With DMA, CPU only initiates transfer (source, destination, count) and gets interrupt on completion; it is free to do other work meanwhile.

2. Why Needed?

• Transfers large blocks (disk, display, ADC) at high speed (MB/s).
• Frees CPU: CPU involvement is O(1) vs O(n) for programmed I/O.
• Overcomes speed mismatch: peripheral can burst at memory speed via bus mastering.

3. Block Diagram

              +-----+   Bus Request/Grant
              | CPU |-----------------+
              +-----+                 v
                 |   +----------+  +------+  +--------+
                 +-->|  DMAC    |<->|Memory|<->|Peripheral|
                     | - Address|<->|      |  | (Disk) |
                     |  Counter |  Data/Addr Bus |
                     | - Word   |  +------+  +--------+
                     |  Count   |
                     | - Control|
                     +----------+
  CPU programs: Source Addr, Dest Addr, Count, Mode (Read/Write)

Inside DMAC: Address Register, Word Count Register, Control/Status Register, Data Buffer.

4. How DMA Transfer Works (Cycle Stealing / Burst Mode)

Steps:

1. Program: CPU writes to DMAC registers: Memory start address, I/O port/device ID, block length (word count), direction (Memory->Device or Device->Memory). Also programs peripheral.

2. Request: Peripheral ready (e.g., disk sector buffered) asserts DMA Request (DRQ) to DMAC.

3. Bus Request: DMAC asserts Bus Request (BR/HOLD) to CPU.

4. Bus Grant: CPU finishes current bus cycle, tristates its buses, asserts Bus Grant (BG/HLDA) and suspends.

5. Transfer: DMAC now bus master:

   • Puts address on address bus (incrementing each word)
   • Generates MEM READ + I/O WRITE (or vice versa) control signals
   • Data moves directly Memory <-> Peripheral via data bus, without going through CPU.
   • Word Count decremented, Address incremented. Repeat each bus cycle.

   Two modes:

   • Cycle Stealing: DMAC takes one bus cycle at a time, interleaving with CPU.
   • Burst/B block transfer: DMAC holds bus for entire block (CPU idle).

6. Completion: When Word Count = 0, DMAC deasserts BR, asserts interrupt DMA Complete to CPU. CPU regains bus.

7. CPU ISR: Reads status, checks error.

5. DMA Transfer Types

• Single Transfer (Flyby): Data flies from source to destination in one bus cycle (Memory and I/O strobes together).
• Two-cycle: Data latched in DMAC buffer first then written.

Modes: Block, Demand, Cascade (multiple DMACs chained, e.g., 8237).

6. Advantages / Disadvantages

Adv: High speed near memory bandwidth, low CPU overhead, ideal for disk, GPU, network.
Disadv: Needs DMAC hardware, bus arbitration logic, cache coherence issue (DMA modifies memory behind cache - needs snooping/flush), cycle stealing slightly slows CPU.

Modern systems use Bus Mastering DMA where peripherals themselves contain DMAC (e.g., PCIe devices become bus masters).

Example: Disk read of 4KB: CPU issues DMA Read 4KB from LBA 100 to 0x2000, continues computation; DMAC moves 4096 bytes at ~100 MB/s; CPU interrupted only at end vs 4096 interrupts otherwise.