Solution - Hardwired vs Microprogrammed Control & Hardwired Organization

A) Difference between Hardwired and Microprogrammed Control Unit:

Basis	Hardwired Control	Microprogrammed Control
Implementation	Combinational logic: gates, flip-flops, decoders, encoders	Control memory (ROM/RAM) storing microinstructions (firmware)
Speed	Very fast (no memory access)	Slower (requires control memory fetch)
Flexibility	Inflexible - modification requires rewiring/redesign	Flexible - just change microprogram in control memory
Complexity	Becomes very complex and difficult to design if instruction set is large	Simple, systematic design even for complex instruction set (CISC)
Cost	Costly for complex ISAs	Cheaper for complex ISAs
Control Signals	Generated directly by hardware	Generated by microinstructions (MW)
Used in	RISC processors, simple CPUs	CISC processors (e.g., x86), older IBM 360
Modification	Difficult to add new instruction	Easy - add new routine to control store

B) Hardwired Control Unit Organization - Components:

A hardwired CU generates control signals as Boolean functions of inputs: Instruction Register (IR), Flags/Condition Codes, Timing signals (T1..Tn) from sequencer, Clock.

Block diagram components:

1. Instruction Register (IR) and Decoder:
   Opcode from IR is decoded by instruction decoder to set one of $2^n$ lines (one per instruction). This selects the required sequence of control signals.

2. Timing Generator / Sequence Counter (SC) and Control Counter:
   Clock pulses are counted by a 4-bit ringJohnson counter or sequence counter that generates time states $T_0, T_1, T_2, T_3 ...$. Each instruction executes as sequence of micro-operations in successive T-states.

3. Control Logic Gates / Encoder:
   Combinational logic (AND-OR gates or PLA) combines decoder output ($I_i$), T-state ($T_j$) and flags ($Z,C$) to generate individual control signals:
   Example: $LoadPC = T_1 \cdot FETCH + T_2 \cdot BRANCH \cdot Z$

4. Flags / Condition Code Register:
   Provides status (Zero, Carry, Sign) to alter control sequence - e.g., for conditional branching or skip.

5. Mode / Processor Status Register:
   Indicates addressing mode, interrupt enable etc. to modify control generation.

Operation:
For each $T_x$ pulse, decoder output and flags are combined in the encoder matrix to assert required signals e.g., $PC_{out}, MAR_{in}, Read, IR_{in}, AC_{in}$ etc. After last T-state, SC is reset to $T_0$ and next instruction fetch starts.

Advantages: High speed. Disadvantage: No flexibility, complex design and testing.