Asynchronous Data Transfer

Transfer where source and destination do not share a common clock. Timing is established by control signals rather than clock edges, allowing devices with different speeds to communicate and eliminating clock-skew problems, at cost of extra handshaking overhead.

Used for slow I/O, inter-system bus (Unibus), UART, etc.

Two schemes:

1. Strobe Control (Single control line)

One STROBE signal times the data.

• Source-initiated strobe:

  1. Source places data on data bus.
  2. After $t_{setup}$ (data stable), source asserts STROBE (e.g. high pulse).
  3. Destination on strobe edge latches data.
  4. Source de-asserts strobe and removes data after hold time.
     Waveform: DATA valid → STROBE ↑ → Dst latches → STROBE ↓
     Risk: No acknowledgement; source assumes worst-case propagation+setup hold time. If destination not ready, data lost.

• Destination-initiated strobe:

  1. Destination asserts STROBE requesting data.
  2. Source places data on bus, informs (no explicit ack).
  3. Destination latches on data valid (uses delay or timeout).
     Similar limitation: no feedback.

Advantage: Simple, 1 wire. Disadvantage: No handshake → needs known timing, cannot handle variable-latency slave.

2. Handshaking (Two-wire, fully interlocked)

Adds REPLY / ACK to guarantee transfer. Two variants:

a) Source-initiated handshaking (most common):

Source                      Destination
  | Data valid on bus            |
  |----------------------------->|
  | STROBE (Data Ready) -------->| 
  |                              | latch data
  | <-------- ACK / Data Accepted|
  | STROBE ↓                     |
  | <-------- ACK ↓ (idle)       |

Sequence:

1. Source: DATA valid → STROBE=1 (Request).
2. Destination: when ready and data latched, asserts ACK=1.
3. Source sees ACK=1, de-asserts STROBE=0, removes data.
4. Destination sees STROBE=0, de-asserts ACK=0 → ready for next.

b) Destination-initiated handshaking:
Roles reversed: Destination initiates REQ / Ready for Data, source responds with Data Valid as ack.

Handshaking is fully interlocked - each edge waits for response, so works for any speed mismatch. Double-handshake (four-event) eliminates races.

Comparison:

Feature	Strobe	Handshaking
Lines	1	2
Feedback	No	Yes
Speed adaptive	No	Yes
Hardware	Minimal	More flip-flops
Use	Fast known delay (e.g. memory)	Variable I/O, bus arbitration

Diagram should show two control lines plus data bus with the four-phase pulse sequence labelled.