Direct Memory Access (DMA)

Why DMA?

Programmed I/O and interrupt-driven I/O transfer word-by-word via CPU, executing IN/OUT instructions and busy-waiting. For bulk transfers (disk, display) this wastes CPU cycles. DMA allows peripheral to transfer block of data directly between I/O device and memory, bypassing CPU except for setup and completion.

CPU initiates DMA, then continues other work; DMA controller (DMAC - e.g. Intel 8237, controller in modern chipsets) steals bus cycles (cycle stealing) or bursts.

Block Diagram - DMA Circuitry

CPU --- Address Bus --------------------------> Memory
 |      Data Bus ----------------------------> Memory
 |      Control Bus (MEMRD/MEMWR, IOR/IOW)   |
 |                                          |
 |  ┌─────────────────────────────────┐     |
 └──┤ DMA Controller (DMAC)           ├─────┘
     │  • Address Reg (start)        │  HRQ→ CPU HOLD
     │  • Word Count Reg             │  HLDA← CPU
     │  • Control Reg (R/W, mode)    │  DREQ← Peripheral (DMA Request)
     │  • Bus buffers & timing       │  DACK→ Peripheral (DMA Ack)
     └──────┬────────────────────────┘
            | DREQ/DACK, Data bus via buffers
       Peripheral Device (Disk, etc.)

Key registers inside DMAC (per channel):

• Address Register - starting memory address, auto-increment/decrement after each word.
• Byte/Word Count Register - decrements to 0 → terminal count (TC) → interrupt.
• Control/Status Register - direction (read/write), mode (burst, cycle-steal, transparent), auto-init.
• Bus Request/Grant Logic

Operation Sequence

1. Init: CPU programs DMAC via I/O writes: load MAR, WC, control. CPU also loads peripheral command.
2. Request: Peripheral ready → asserts DREQ.
3. Handshaking: DMAC asserts HRQ (Hold Request) to CPU. CPU finishes current bus cycle, tristates address/data/control, asserts HLDA (Hold Ack). DMAC becomes bus master.
4. Transfer: DMAC puts memory address on address bus, asserts MEMRD (for I/O→Mem) or MEMWR (Mem→I/O) + DACK+IOR/IOW to device; data flows directly Device↔Memory without CPU register. After each word: MAR++, WC--.
5. Termination: When WC==0, DMAC asserts TC and optionally interrupts CPU (TC/INT), releases HRQ, CPU regains bus.

Transfer Modes

• Burst/Block: Holds bus until entire block done (fast, CPU blocked).
• Cycle-stealing: Transfers one word per bus cycle stolen between CPU cycles (common).
• Transparent: Only when CPU not using bus.

Advantages

• Speed: memory-limited (no instruction fetch/decode per word) → $10\text{-}100\times$ faster.
• CPU free for computation, overlapped I/O.

DMA vs Interrupt

Interrupt still needs CPU per word; DMA needs CPU only twice (setup + completion interrupt).