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COMPUTER ORGANIZATION & ARCHITECTUREThe performance of a pipelined processor suffers if (i) The pipeline stages have different delays (ii) Consecutive instruction are dependent on each other (iii) The pipeline stages share hardware resources (iv) All of these20232mDIGITAL ELECTRONICSWrite the difference between combinational and sequential circuits.20232mCOMPUTER ORGANIZATION & ARCHITECTUREIn case of pipelining processor, loop buffer is * (i) very high speed memory maintained by the instruction fetch stage * (ii) very high speed memory maintained by the instruction decode stage * (iii) very high speed memory maintained by the instruction execute stage * (iv) None of the above20192mCOMPUTER ORGANIZATION & ARCHITECTUREPipeline speedup ideally increases with: (i) Number of control units (ii) Size of RAM (iii) Number of pipeline stages (iv) Size of cache20252m
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