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COMPUTER ORGANIZATION & ARCHITECTUREThe average memory access time for a machine with a cache hit rate of 90% where the cache access time is 10 ns and the memory access time is 100 ns is * (i) 55 ns * (ii) 45 ns * (iii) 90 ns * (iv) 19 ns20192mOperating SystemConsider a paging hardware with a TLB. Assume that the entire page table and all the pages are in the physical memory. It takes 10 milliseconds to search the TLB and 80 milliseconds to access the physical memory. If the TLB hit ratio is 0.6, find the effective memory access time (in milliseconds).20227mOPERATING SYSTEMConsider a demand-paging system with a paging disk that has an average access and transfer time of 20 milli-seconds. Addresses are translated through a page table in main memory, with an access time of 1 microsecond per memory access. Thus, each memory reference through the page table takes two accesses. To improve this time, we have added an associative memory that reduces access time to one memory reference if the page-table entry is in the associative memory. Assume that 80 percent of the accesses are in the associative memory and that of those remaining, 10 percent (or 2 percent of the total) cause page faults. What is the effective memory access time?20227mCOMPUTER ORGANIZATION & ARCHITECTUREHow do instruction set, compiler technology, CPU implementation and control, and cache and memory hierarchy affect the CPU performance? Justify the effects in terms of program length, clock rate and effective CPI.20197m
PreviousThe performance of a pipelined processor suffers if (i) The pipeline stages have different delays (ii) Consecutive instruction are dependent on each other (iii) The pipeline stages share hardware resources (iv) All of theseNextWhich of the following has no practical usage? (i) SISD (ii) SIMD (iii) MISD (iv) MIMD