4-bit Carry Look-Ahead Adder (CLA)

Problem with Ripple Carry: Carry propagates serially: $C_{i+1}$ waits for $C_i$ -> delay $O(n)$, $4\times2\Delta$ gates.

CLA generates all carries in parallel using $G$ (generate) and $P$ (propagate).

For bit $i$: $A_i, B_i, C_i$

$$G_i = A_i \cdot B_i$$
$$P_i = A_i \oplus B_i \quad (\text{or } A_i+B_i)$$

Sum: $S_i = P_i \oplus C_i$
Carry: $C_{i+1}= G_i + P_i C_i$

Design Equations ($C_0$ = input carry)

$$C_1 = G_0 + P_0 C_0$$
$$C_2 = G_1 + P_1 G_0 + P_1 P_0 C_0$$
$$C_3 = G_2 + P_2 G_1 + P_2 P_1 G_0 + P_2 P_1 P_0 C_0$$
$$C_4 = G_3 + P_3 G_2 + P_3 P_2 G_1 + P_3 P_2 P_1 G_0 + P_3 P_2 P_1 P_0 C_0$$

Hardware: 4 G/P gates (1 level), 4 carry AND-OR networks (2 levels), 4 XOR for sum -> total delay ~ $3\Delta$ independent of $n$ (vs $8\Delta$ for RCA).

Block Diagram: $A[3:0], B[3:0]$ -> G/P generator -> CLA logic (generates $C_1$-$C_4$) -> XOR -> $S[3:0]$, $C_4$ is Cout. Draw 2-level AND-OR.

Example: Add $A=1011$ (11) + $B=0101$ (5), $C_0=0$ -> Expect $10000$ (16)

i	$A_i$	$B_i$	$G_i$	$P_i$
0	1	1	1	0
1	1	0	0	1
2	0	1	0	1
3	1	0	0	1

Compute:
$C_1 = 1+0\cdot0=1$
$C_2 = 0+1\cdot1=1$
$C_3 = 0+1\cdot0+1\cdot1\cdot1=1$
$C_4 = 0+1\cdot0+1\cdot1\cdot0+1\cdot1\cdot1\cdot1+1\cdot1\cdot1\cdot0\cdot0=1$

Sums: $S_0=0\oplus0=0$, $S_1=1\oplus1=0$, $S_2=1\oplus1=0$, $S_3=1\oplus1=0$ + $C_4=1$ => $10000$.

All carries generated simultaneously -> ~3 gate delays. For wider adders, use hierarchical CLA (4-bit blocks with block $G^*, P^*$).