Carry Look-Ahead Adder (CLA)

Problem with Ripple Carry Adder (RCA): $C_{i+1}= G_i + P_i C_i$ propagates sequentially → delay $O(n)$ (≈ $2n$ gate delays for $n$ bits).

CLA solves by computing all carries in parallel using Generate ($G$) and Propagate ($P$).

For each bit $i$:

• $G_i = A_i \cdot B_i$ (generate – carry created)
• $P_i = A_i \oplus B_i$ (propagate – carry passed; some use $A_i+B_i$)
• $Sum_i = P_i \oplus C_i$
• $C_{i+1}= G_i + P_i C_i$

Expanding:

• $C_1 = G_0 + P_0 C_0$
• $C_2 = G_1 + P_1 G_0 + P_1 P_0 C_0$
• $C_3 = G_2 + P_2 G_1 + P_2 P_1 G_0 + P_2 P_1 P_0 C_0$
• $C_4 = G_3 + P_3 G_2 + P_3 P_2 G_1 + P_3 P_2 P_1 G_0 + P_3 P_2 P_1 P_0 C_0$

All $C_i$ after 2 levels of AND-OR, independent of ripple.

1-bit CLA slice

A_i --+--\
      |   XOR --> P_i ----+--> XOR --> Sum_i
B_i --+--/   AND --> G_i -+      ^ 
                     |          C_i

Carry look-ahead logic block generates $C_{i+1}$ from $G_i, P_i, C_i$.

4-bit CLA Block (with group GG, GP)

        +-----------------------------------+
C0 ---> | CLA Logic | ---> C1 C2 C3 C4      |
A3-0 B3-0 -> P3-0 G3-0                       |
        +-----------------------------------+
         P* = P3 P2 P1 P0
         G* = G3 + P3 G2 + P3 P2 G1 + P3 P2 P1 G0

8-bit CLA using two 4-bit CLA blocks (or eight 1-bit slices)

Method: Two 4-bit CLA modules cascaded with ripple of group carry (or full 2-level CLA):

C0 --> [ 4-bit CLA 0 ] -- C4 --> [ 4-bit CLA 1 ] -- C8
       A0-3 B0-3 S0-3           A4-7 B4-7 S4-7
       | P0* G0*               | P1* G1*
       +-----------+-----------+
                   |
            CLA Lookahead for C4
      C4 = G0* + P0* C0
      C8 = G1* + P1* G0* + P1* P0* C0

Diagram (8-bit):

                +------------------+   +------------------+
C0 ------------->| 4-bit CLA      |-->| 4-bit CLA        |--> C8
A0 B0 -> P0 G0 ->| S0 = P0 xor C0 |   | S4 = P4 xor C4   |
A1 B1 -> P1 G1 ->| S1 = P1 xor C1 | C4| S5 = P5 xor C5   |
A2 B2 -> P2 G2 ->| S2 = P2 xor C2 |-->| S6 = P6 xor C6   |
A3 B3 -> P3 G3 ->| S3 = P3 xor C3 |   | S7 = P7 xor C7   |
                +------------------+   +------------------+
                  G0* P0*                  G1* P1*

Using eight 1-bit CLA slices: Each slice provides $P_i,G_i$; central CLA generator computes $C_1..C_8$ in parallel from all $P,G$ and $C_0$, then each sum $S_i = P_i \oplus C_i$.

Advantages: Delay $O(\log n)$ vs $O(n)$; 8-bit delay ≈ 4-6 gates vs 16 for RCA. Cost: more gates (AND-OR fan-in), fan-in limits for large $n$ → hierarchical CLA (4-bit groups).

Trade-off: CLA faster, more hardware; RCA smaller, slower.