Addition / Subtraction Algorithm (Binary, 2's complement) – Flowchart

Uses registers: $A$ (accumulator), $B$, $Q$? For simple $A \pm B$.

Algorithm:

1. For addition: $A \leftarrow A + B$ using binary adder.
2. For subtraction: $A \leftarrow A - B = A + (\bar{B}+1)$ (2's complement of B).
3. Detect overflow: $V = C_{n} \oplus C_{n-1}$ (carry into sign xor carry out of sign).

Flowchart (Text)

           START
             |
             v
     +-----------------+
     | Load A = Augend |  
     |      B = Addend |
     +--------+--------+
              |
     +--------v--------+
     | Operation?      |---- SUB ----> B = ~B + 1 (2's comp)
     | ADD / SUB       |              (or SUB = ADD with Cin=1)
     +--------+--------+
              | ADD
              v
     +-----------------+
     | A = A + B       |
     | (parallel adder)|
     +--------+--------+
              |
     +--------v--------+
     | Overflow?       |--- Yes ---> Set V=1, Trap/Indicate
     | V = Cn xor Cn-1 |
     +--------+--------+
              | No
              v
     +-----------------+
     | Result in A,    |
     | Carry C, V flag |
     +--------+--------+
              |
             END

Detailed Step for Subtraction via Adder

SUB:  B' = NOT B
      Cin = 1
      Sum = A + B' + Cin
Equivalent to A + (2's complement of B)

4-bit Example

$A=0101 (+5)$, $B=0011 (+3)$

• ADD: $0101+0011=1000$ (8, overflow if signed 4-bit? $V=1$ because positive+positive=negative)
• SUB: $A-B =0101 +1101 =0010$ (+2) ($1101$ is -3)

Hardware: Uses $n$-bit parallel adder (ripple/CLA) with XOR gates on $B$ controlled by $SUB$ signal: $B_i \oplus SUB$, $Cin=SUB$.

Overflow logic: If $A_{n-1}, B_{n-1}$ same and $Sum_{n-1}$ different → overflow.

For magnitude (sign-magnitude) algorithm, extra step compares signs and magnitudes, but 2's complement above is standard in ALU.