Short Note: Paging (7 Marks)

Concept: Paging is a memory management scheme that eliminates external fragmentation by dividing logical memory into fixed-size pages and physical memory into same-size frames. Pages are mapped to available frames via page table.

Terminology: Page size power of 2 (512B-8KB typical, e.g., 4KB in x86). Logical address = | Page Number (p) | Offset (d) |. Physical address = | Frame Number (f) | Offset (d) |.

Mechanism:

• CPU generates logical address. MMU extracts $p$ and $d$.
• Page Table (per process, in RAM) gives $p \to f$ mapping. Accessed via Page Table Base Register (PTBR).
• Physical address = $f \times \text{pageSize} + d$. Translation via TLB cache for speed.

Page Table Entry contains: Frame number, valid/invalid bit, protection (R/W/X), dirty, referenced, present bit.

Example: 16-bit logic, page 1KB (10 bits offset): | p(6) | d(10) |. If $p=2$ maps to $f=7$, logic 00 0010 00 0000000000 → physical 00 0111 00....

Types:

• Single-level: Simple but large for 32-bit (1M entries).
• Multi-level/Hierarchical paging (2/3-level): Used in x86 (Page Directory → Page Table), reduces table size.
• Inverted Page Table: One entry per frame, for large address spaces.

Advantages: No external fragmentation, simple allocation, supports virtual memory and swapping (pages to disk), protection and sharing (shared frames).

Disadvantages: Internal fragmentation (last page waste avg ½ page), page table memory overhead, translation overhead (TLB miss penalty), needs TLB for performance.

Demand Paging: Pages loaded from disk only on page fault (valid=0) → supports virtual memory larger than physical, uses page replacement (FIFO/LRU).

Paging vs Segmentation: paging fixed size, invisible to programmer; segmentation variable, logical units.