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Module 2: x86 Architecture, CPU Control, I/O, Memory System Design

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Write short notes on: Privileged and non-privileged instructions

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Privileged vs Non-Privileged Instructions [7M]

Context: Modern OS must protect itself, memory and devices from user programs. CPU provides dual-mode operation: Supervisor/Kernel mode (privileged) and User mode (non-privileged). Mode indicated by PSW bit (e.g. x86 CPL / PE flag, ARM M bits). Some instructions allowed only in supervisor mode.

1. Privileged Instructions:

Define: Executable only when CPU in supervisor mode (mode=0mode=0). If attempted in user mode, triggers privileged instruction trap / General Protection Fault.

  • Examples:

    • I/O instructions: IN, OUT, INS, OUTS (x86), HLT, CLI, STI (halt, disable/enable interrupts)
    • Control registers: MOV CR0, EAX, LIDT, LGDT, WRMSR, TLB flush (INVLPG)
    • Memory management: LMSW, MOV to CR3 (page table base)
    • Interrupt & DMA control: IRET, enable/disable DMA
    • HALT, RESET processor
  • Purpose: Directly manipulates shared hardware resources. Only OS kernel should do that.

2. Non-Privileged (Unprivileged / User) Instructions:

Executable in any mode. Ordinary computation not affecting system state.

  • Examples: MOV, ADD, SUB, MUL, CMP, JMP, CALL, PUSH, POP (within user stack), floating point arithmetic.
  • Some sensitive but non-privileged: e.g. POPF may not allow changing interrupt flag if in user mode (x86 masks it).

3. Why distinction? Protection

  • Prevents user program from: corrupting other processes' memory (via MMU), stealing devices, masking interrupts, halting system, changing scheduling.
  • System calls: User wants I/O -> executes trap / INT 0x80 / SYSCALL which switches to kernel mode, OS validates parameters then executes privileged operation on behalf.
  • Virtualization: Hypervisor uses privileged instructions to emulate hardware for guest.

4. Mechanism:

Hardware checks mode bit before decoding. E.g. pseudo:

if (instruction.isPrivileged && PSW.mode == USER) -> exception(13)

x86 has 4 rings (0=kernel most privileged, 3=user). I/O privilege level (IOPL) in EFLAGS controls IN/OUT access. ARM has SVC (supervisor) vs USR.

Comparison Table:

Aspect Privileged Non-privileged
Mode Kernel only User & Kernel
Function System control Computation
Trap if violated Yes - #GP fault No
Example HLT, CLI, IN, LGDT ADD, MOV, AND

Without this separation, multi-programming and OS isolation would be impossible.

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