Why Read ($\overline{MEMR}$/$\overline{IOR}$) and Write ($\overline{MEMW}$/$\overline{IOW}$) Lines in DMA Controller are Bidirectional [14 Marks]

1. Background - 8237 / Generic DMAC and Bus Master Concept

System bus has control lines $\overline{MEMR}$, $\overline{MEMW}$, $\overline{IOR}$, $\overline{IOW}$ (or unified $\overline{RD}$, $\overline{WR}$). Normally CPU is bus master and drives these lines as outputs to command memory/I/O.

During DMA, DMAC becomes bus master after Bus Request ($HRQ$/$BUSREQ$) → Bus Grant ($HLDA$/$BUSACK$) handshake. The direction of $\overline{RD}$/$\overline{WR}$ reverses depending on who is master.

Hence DMAC pins are bidirectional (open-drain with direction control): sometimes input, sometimes output.

2. When DMAC is Bus Slave - Lines are INPUTS

Condition: CPU is bus master, DMAC is not performing DMA (Idle or Programming mode). CPU addresses DMAC as an I/O device via its chip select ($\overline{CS}$) and register addresses (A0-A3).

Purpose as Inputs: CPU programs DMAC's internal registers:

• DMA Address Register (starting address)
• Terminal Count / Word Count Register
• Mode Register, Command Register, Mask Register, Request Register

Operations:

• CPU performs I/O Write to DMAC: $\overline{IOW}$ (= $\overline{WR}$) = 0 as input to DMAC + $\overline{CS}$=0 → data D0-D7 latched into DMAC register. Example: OUT 0BH, AL to write Mask Register.
• CPU performs I/O Read from DMAC: $\overline{IOR}$ (= $\overline{RD}$) = 0 as input → DMAC drives data bus with status / remaining count register contents for CPU to read. Example: IN AL, 08H to read Status Register.

Without input mode, CPU could not initialize DMA channel (source, destination, count, transfer type) before starting.

3. When DMAC is Bus Master - Lines are OUTPUTS

Condition: DMAC has acquired bus ( $HLDA=1$, $AEN=1$, CPU tristates its buses). Now DMAC drives address bus and control lines to perform data transfer between Memory and I/O without CPU.

Purpose as Outputs - Two Types of DMA Transfer:

• DMA Read (Memory → Peripheral): DMAC asserts $\overline{MEMR}$ (or $\overline{RD}$ as output, low) to read memory and $\overline{IOW}$ to write to I/O device in same bus cycle (or two cycles in flyby vs. two-cycle DMA). Data flows memory → DMAC → I/O.
• DMA Write (Peripheral → Memory): DMAC asserts $\overline{IOR}$ to read peripheral and $\overline{MEMW}$ to write to memory. Data flows I/O → memory.
• Memory-to-Memory (in 8237): $\overline{MEMR}$ and $\overline{MEMW}$ sequentially asserted.

Thus as outputs, they act exactly as CPU's control signals would, commanding the memory and I/O participants.

4. Summary Diagram (Conceptual)

         CPU (Master)  -------- IOR/IOW / MEMR/MEMW --------> DMAC (Slave) : INPUT mode (Program)
                                         |
         DMAC (Master) -------- MEMR/MEMW , IOR/IOW --------> Memory & I/O : OUTPUT mode (Transfer)
                              (controls bus)

Internal direction control via Bus Master Enable logic: when $HLDA=1$ & $AEN$ active → buffers set to output; otherwise inputs. Shared pins save package pins and reflect that bus control is mutually exclusive - only one master drives at a time.

Key Advantage: Single set of control lines serves dual role → reduces interconnect and allows seamless hand-shaking: CPU configures DMAC as peripheral, then DMAC uses same lines as master to orchestrate high-speed block transfers (≈ 1.6 MB/s in 8237), freeing CPU.

Exam Tip: Always mention both modes with concrete instruction example (OUT/IN) for input, and Flyby transfer example for output.