DMA Cycle Stealing Slowdown Calculation [7M]

Given: DMA transfers 16-bit words using cycle stealing. Device transmits characters at 2400 chars/sec. Characters assumed 8-bit (1 byte). CPU average 1 million instructions/sec (1 MIPS). Assume 1 instruction = 1 memory cycle stolen per DMA word. Find slowdown %.

Understanding cycle stealing: DMA steals one bus/memory cycle from CPU per word. CPU pauses (or bus is held) for that cycle, so instruction rate reduces proportionally.

Step 1: DMA word rate

Device rate = 2400 characters/s = 2400 bytes/s

Words are 16-bit = 2 bytes = 2 characters per word (assembled)

So word assembly rate:

$$f_{DMA} = \frac{2400 \text{ chars/s}}{2 \text{ chars/word}} = 1200 \text{ words/s}$$

Each word needs one steal cycle.

Step 2: CPU cycles

Assume CPU fetch-execute average needs 1 memory cycle per instruction => 1 MIPS = $1 \times 10^6$ cycles/s demanded.

Step 3: Fraction stolen

$$\text{Fraction} = \frac{\text{DMA cycles stolen per sec}}{\text{Total CPU cycles per sec}} = \frac{1200}{1\,000\,000} = 0.0012$$

Percentage slowdown:

$$0.0012 \times 100 = 0.12\%$$

Alternate interpretation if each instruction itself takes multiple cycles (e.g. 4 cycles avg) vs steal of one bus cycle ~1 cycle, then instruction slowdown = $1200/(4 \times 10^6)$? But problem states average instruction rate not clock rate, and 1 word = 1 instruction-equivalent slot, so above is expected answer.

Result:

CPU slowed by 0.12 % - negligible ($\approx 1200$ cycles stolen per second).

If DMA burst mode instead of cycle steal were used, CPU would be blocked for contiguous 1200 cycles ($\approx 1.2 ms$) per second.

General formula:

$$\%\text{slowdown} = \frac{\text{Device throughput (bytes/s)}}{\text{bytes/word}} \times \frac{1}{\text{MIPS}} \times 100$$

Even at 240k chars/s (100x faster), slowdown only 12% - justifies cycle stealing for slow character devices.

Note: If character = 16-bit word (i.e. device directly gives 2400 words/s), then $2400/10^6 = 0.24\%$ slowdown. With given answer 0.12% exam expects 2 chars/word assembly, hence 1200 words/s.