Control Unit of Basic Computer (Mano)

Hardwired control unit generates signals for registers, memory, ALU timed by Sequence Counter (SC) $T_0$ to $T_{15}$.

Block Diagram (Textual)

                    +-------------------+
Clock --------------| Sequence Counter  |---- T0..T15 (decoded)
Reset -------------|   SC (4-bit)      |
                    +---------+---------+
                              | Increment / Clear
                              v
  Opcode (IR12-14) ->+--------+--------+      +--------------+
  I bit (IR15) ------> Decoder (3x8)  |----->| Control Logic|
                     +--------+--------+      |  Gates       |--- Control signals:
  T0-T7 ------------->                       |  (AND-OR)    |    LDAR,LDPC,LDAC,LDDR,LDAC
  Flags(E,AC,etc) --->                       +------+-------+    RD/WR,MEM, INCPC, CLRSC...
                                                    |
  IR 0-11 Address ----------------------------------+

Components:

1. Sequence Counter SC: 4-bit counts $0$ to $15$, decoded to $T_i=1$ only at that count.
2. Instruction Register IR(15-0): IR(12-14)→ 3x8 decoder gives $D_0$-$D_7$, IR(15)=$I$, IR(11-0)= address.
3. Control Logic Gates: Combine $D_i \cdot T_j \cdot I/\bar I$ and flags to produce register transfer signals.

Control Timing Diagrams

Sequence for every instruction: Fetch ($T_0$-$T_1$), Decode ($T_2$), Execute ($T_3$-$T_7$).

Time	Micro-operations	Control signals
$T_0$	$AR \leftarrow PC$	$PC_{out}, AR_{in}$
$T_1$	$IR \leftarrow M[AR], PC \leftarrow PC+1$	$MEM_{read}, IR_{in}, PC_{inc}$
$T_2$	$D_0..D_7 \leftarrow Decode IR(12-14)$,<br>$AR \leftarrow IR(11-0)$,<br>$I \leftarrow IR(15)$	$Decode, AR_{in}$
$T_3$	Memory-ref with I=1: $AR\leftarrow M[AR]$ (indirect)	$MEM_{read}, AR_{in}$
	Register-ref ($D_7,I=0$): Execute $rB_i$ (e.g. $CLA$) and $SC\leftarrow0$	$r\cdot T_3$
	I/O ($D_7,I=1$): Execute $pB_i$	$p\cdot T_3$
$T_4$	$D_0 T_4$: $DR\leftarrow M[AR]$ (AND)<br>$D_1 T_4$: $DR\leftarrow M[AR]$ (ADD)...	$MEM_{read}, DR_{in}$
$T_5$	$D_0 T_5$: $AC\leftarrow AC\land DR,\; SC\leftarrow0$<br>$D_1 T_5$: $AC\leftarrow AC+DR,\; E\leftarrow C_{out},\; SC\leftarrow0$<br>$D_2 T_4$: $AC\leftarrow DR$ etc.	$AC_{in}, CLRSC$
$T_6$	For BSA, ISZ etc.

Timing diagram sketch:

Clock _|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_
SC    0   1   2   3   4   5   0 ...
T0    ‾‾|__ ____________________
T1    __|‾‾|__ _________________
T2    ____|‾‾|__ _______________
T3    ______|‾‾|__ ____________
D7·T3 triggers register micro-op and clears SC -> next Fetch.
D0·T4, D0·T5 etc. shown as narrow pulses.

Example - ADD direct (D1,I=0):
$T_0: AR<-PC$, $T_1: IR<-M[AR],PC++$, $T_2: Decode$, $T_3: idle$, $T_4: DR<-M[AR]$, $T_5: AC<-AC+DR, E<-carry, SC<-0$.

Example - CLA (D7,I=0,B11=1):
$r = D_7 \cdot \bar I \cdot B_{11}$, $rT_3: AC<-0, SC<-0$ single cycle.

Hardwired version uses gates; microprogrammed version would store above $T_iD_j$ combinations in control memory.