Functional Blocks of a Computer - CPU, Memory, I/O with Diagram (7M)

Derived from Von Neumann Stored Program concept. Four main functional blocks interconnected by System Bus.

                    +----------------------------+
                    |      Central System Bus    |
                    |  Address | Data | Control  |
                    +----+-------------+----+----+
                         |             |    |
        +----------------+ +-----------+ +--+-----------+
        |   CPU          | |  Memory   | | I/O Module   |
        | +------------+ | | +-------+ | | +----------+ |
        | | Control    | | | |  RAM   | | | Control  | |
        | | Unit (CU)  | | | | (R/W)  | | +----+-----+ |
        | +------------+ | | +-------+ | |      | I/O  |
        | | ALU        | | | |  ROM   | | +----+-----+ |
        | | (ADD,SUB,  | | | |  Cache | | | Device | |
        | |  AND,OR)   | | | +-------+ | | |Controller|<---> Peripheral
        | +------------+ | |            | | +----------+ |  (Keyboard,
        | | Registers  | | |            | |              |   Display, Disk)
        | | PC,IR,MAR, | | |            | +----------------+
        | | MDR,GPR,SP | | |            | 
        | +------------+ | |            |
        | | Internal Bus | |            |
        +----------------+ +-----------+ +----------------+
                                          Interconnection via Bus Arbitration

1. Central Processing Unit (CPU) / Processor

Heart & Brain - fetches, decodes, executes instructions and coordinates.

a) Control Unit (CU):
Generates control signals, sequencing fetch-decode-execute. Controls data flow between blocks via control bus (MEMR, MEMW, IOR, IOW, CLK). Two implementations: Hardwired (fast, for RISC) and Microprogrammed (flexible, for CISC - stores microinstructions in control memory).

b) Arithmetic Logic Unit (ALU):
Executes arithmetic (ADD, SUB, MUL, DIV, INC), logical (AND,OR,XOR,NOT), shift/rotate. Contains adder, shifter, status flags (CF,ZF,SF,OF). Operates on registers.

c) Register Organization:
Fast internal storage (ns access):

• User-visible: GPRs (AX,BX,CX,DX in 8086; R0-R15 in ARM), Data/Address registers.
• Control & Status: PC (Program Counter / IP) holds next instruction address, IR (Instruction Register) holds current opcode, MAR (Memory Address Register), MDR/MBR (Memory Data Register), SP (Stack Pointer), PSW/FLAGS.
• Internal bus connects them with ALU.

Function cycle: PC->MAR, Memory fetch to MDR->IR, decode, execute with ALU, writeback to register/memory.

2. Memory Unit

Stores program (instructions + data) - volatile main memory plus hierarchy.

• Main Memory (Primary): Random Access Memory (RAM) for program/data during execution - DRAM (capacitor, needs refresh, large capacity), SRAM for cache. ROM (Read Only) for boot firmware. Organization M = 2^N words, N=address lines (32-bit => 4GB).
• Cache Memory (L1/L2/L3): Small fast SRAM between CPU & RAM to exploit locality (hits 90%+). Reduces effective access time: T_eff = h*T_cache + (1-h)*T_ram.
• Interface: Address Bus selects cell, Data Bus carries word, Control Bus (MEMR/MEMW). Access via MAR/MDR.

Part of Memory Hierarchy: Registers (fastest, smallest) -> Cache -> Main Memory -> Secondary (Disk) -> Tertiary.

3. Input / Output (I/O) System

Interface between computer internal world and external peripherals.

• I/O Module / Controller: Hardware between bus and device:

  • Data buffering (latch), Address decoding (port select), Control & Timing (device protocol), Error detection.
  • Examples: 8255 PPI, 8251 USART, DMA controller, Graphics card, Disk controller.

• Peripheral Devices:

  • Input: Keyboard, Mouse, Scanner, Mic
  • Output: Monitor, Printer, Speaker
  • Storage I/O: Hard Disk, SSD, USB (both I/O)
  • Network: Ethernet/WiFi card

• Data Transfer Techniques:

  • Programmed I/O - CPU polls device status.
  • Interrupt-driven - device interrupts CPU via INTR.
  • DMA - controller takes bus mastering to move block directly Memory↔Device without CPU per byte.

Interaction Example: Pressing 'A' on keyboard -> I/O controller asserts interrupt INTR -> CU finishes instruction, branches to Interrupt Vector -> ISR reads port 60H via IN AL,60H over buses -> stores in Memory.

4. System Bus - Interconnection

Shared highway; three sub-buses:

• Address Bus (A0-An-1, unidirectional CPU->others): Carries N-bit address to select one of 2^N locations or I/O ports.
• Data Bus (D0-Dm-1, bidirectional): Carries instruction/data word (8/16/32/64-bit). Tri-state.
• Control Bus (mixed direction): Signals: RD*, WR*, CLK, RESET, READY, INTR, NMI, HOLD/HLDA, IOR/IOW, MEMR/MEMW, Bus Request/Grant.

Only one master drives bus at a time - needs bus arbitration.

Information Flow Example (Fetch MOV AX, [2000H]):
PC(=1000H) -> Address Bus, Control=MEMR -> Memory puts opcode at 1000H on Data Bus -> IR loads. Decode -> MAR=2000H -> second read. ALU passes to AX.

Exam drawing: Central bus horizontal, four vertical blocks CPU (detail CU,ALU,Reg), Memory (RAM,ROM,Cache), I/O (module + peripherals) all attached. Label buses and directions.