8-bit Microprocessor Architecture (e.g., 8085) – Block Diagram Description

Block diagram components:

[Address Bus 16-bit] ← Address Buffer ← Program Counter & Stack Pointer
[Data Bus 8-bit] ↔ Data Buffer ↔ Instruction Register & Accumulator
Control Bus ↔ Timing & Control Unit ↔ Clock (Crystal)
CPU: ALU (8-bit) + Flags (S,Z,AC,P,CY), General Registers B,C,D,E,H,L, Temp registers W,Z
Interrupt Control (TRAP,RST7.5,6.5,5.5,INTR)
Serial I/O

Function of blocks:

1. ALU: 8-bit add/sub/logic, with flags.
2. Registers: B-C,D-E,H-L pairs for 16-bit ops, Accumulator, PC (16-bit), SP (16-bit).
3. Timing & Control: Generates RD, WR, ALE, IO/M, FETCH, decode and sequencing.
4. Instruction Decoder & Register: Decodes opcode from IR.
5. Address/Data buffers: Drive external buses.
6. Oscillator: Crystal drives internal clocks (T-states → Machine cycles → Instruction cycles).
   Working: Fetch PC→MAR→address bus, RD low, instruction→MDR→IR, decode, execute with ALU/register/memory, increment PC, handle interrupts. Harvard not applicable, Von Neumann unified memory. This architecture enables fetch-decode-execute loop with stack and interrupts.