8051 Internal Block Diagram – Description

Major blocks:

• CPU: 8-bit ALU + Accumulator + B + PSW flags + Temp registers.
• Program Memory (4KB ROM) + Data Memory (128B RAM) Harvard, separate buses. RAM: 00-1FH 4 banks, 20-2FH bit-addressable, 30-7FH general, 80-FFH SFRs.
• Instruction Register & Decoder, Timing & Control, Oscillator (XTAL1/2): 12-clock machine cycle, generates ALE, \overline{PSEN}, RD, WR.
• Interrupt Controller: 5 sources as before → priority encoder.
• Timer/Counter 0 &1: 16-bit, TMOD/TCON/TH/TL.
• Serial Port: UART with SCON/SBUF, baud via Timer1.
• I/O Ports P0-P3: latches + drivers + pin logic.
• Special Function Registers, DPTR (16-bit), PC (16), SP (8), buses: internal 8-bit data, 16-bit address via P0/P2.

Data flow: Oscillator drives control → fetches via PC→ROM→IR→decode → ALU/SFR/port/timer ops → ports/timers/serial run in parallel. Program and data fetch can overlap via separate buses. Textual diagram sufficient; enumerate connections: ALE→latch, PSEN→ROM, RD/WR→RAM/peripherals.

Sketch: Center CPU, top program ROM via bus, bottom RAM+SFRs, left ports, right oscillator+interrupt+timer+serial.