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Module 2: The 8051 Architecture

20247m

Explain the functions and programming associated to Interrupt Controller block in 8051.

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Interrupt Controller in 8051 – Functions & Programming

Sources (5): INT0 (0003H), Timer0 (000BH), INT1 (0013H), Timer1 (001BH), Serial (0023H). Priority via IP register, enable via IE.

Registers:

  • IE (A8H): EA (global) | - | - | ES | ET1 | EX1 | ET0 | EX0 ; set to enable.
  • IP (B8H): PS | PT1 | PX1 | PT0 | PX0 – 1=high priority.
  • TCON (88H): IT1,IT0 (edge/level), IE1/IE0 (flags), TF1/TF0, TR1/TR0.

Programming:

MOV IE,#10000101B ; EA=1, ES=0, ET1=1, EX1=0, ET0=1, EX0=1 -> enable INT0, T0, T1
MOV IP,#00000001B ; PX0 high priority
SETB IT0 ; edge triggered INT0

Working: When interrupt occurs, flag set, if enabled & priority allows, CPU finishes current instruction, pushes PC, vectors to ISR address, clears flag (TI/RI not auto-cleared), RETI pops PC and restores. Nested interrupts allowed via high priority.

Example ISR stub: ORG 0003H ; LJMP EXT0_ISR.

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