I/O Port Pins Functions in 8051

8051 has 4×8-bit ports (32 lines), each bidirectional with internal pull-ups except P0 open-drain for external memory.

• Port 0 (P0.0-P0.7, pins 32-39): Quasi I/O when internal memory used; Alternate: AD0-AD7 multiplexed address/data bus for external program/data memory. Needs external pull-ups when used as I/O.
• Port 1 (P1.0-P1.7, pins 1-8): Dedicated I/O only (quasi-bidirectional, pull-ups), no alternate. Often for LED, keypad, etc. Some derivatives add alternate (T2, etc.).
• Port 2 (P2.0-P2.7, pins 21-28): I/O plus A8-A15 high address byte for external memory (when P0 low byte latched). Maintains high address during data phase.
• Port 3 (P3.0-P3.7, pins 10-17): I/O plus 8 alternates: P3.0 RxD (serial in), P3.1 TxD (serial out), P3.2 INT0, P3.3 INT1, P3.4 T0, P3.5 T1, P3.6 WR, P3.7 RD. Alternate enabled via SFR bits (SCON, TCON, IE).

Each port SFR (80H,90H,A0H,B0H) latch; reading drives pin state. Writing 1 makes pin input (floating with pull-up) for reading external.