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2024 question paper

MICROPROCESSORS

25 questions

  1. Q1a. The Program Counter (PC) in 8051 is how many bits? (i) 8-bit (ii) 16-bit (iii) 12-bit (iv) 32-bit20242m

    Module 2: The 8051 Architecture

    The Program Counter (PC) in 8051 is how many bits?
    (i) 8-bit
    (ii) 16-bit
    (iii) 12-bit
    (iv) 32-bit

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    Answer: (ii) 16-bit

    Explanation: The Program Counter (PC) in 8051 is a 16-bit register. It holds the address of the next instruction to be fetched. Because 8051 can address up to 64K bytes of program memory (0000H–FFFFH), PC must be 16 bits wide. It is automatically incremented after each fetch and is affected by jumps, calls, and branches.

  2. Q1b. In 8051, which register is used to enable or disable interrupts? (i) IE (ii) IP (iii) TCON (iv) PCON20242m

    Module 2: The 8051 Architecture

    In 8051, which register is used to enable or disable interrupts?
    (i) IE
    (ii) IP
    (iii) TCON
    (iv) PCON

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    Answer: (i) IE

    Explanation: IE = Interrupt Enable register (address A8H) in 8051. Bit EA (IE.7) is the global enable; bits ES, ET1, EX1, ET0, EX0 individually enable/disable serial, Timer1, External1, Timer0, External0 interrupts. IP = Interrupt Priority, TCON controls interrupt flags and timer run, PCON is power control. So IE enables/disables interrupts.

  3. Q1c. Which of the following microcontrollers is based on the Harvard architecture? (i) Intel 8085 (ii) Intel 8086 (iii) Intel 8051 (iv) ARM Cortex20242m

    Module 1: Fundamentals of Microprocessors

    Which of the following microcontrollers is based on the Harvard architecture?
    (i) Intel 8085
    (ii) Intel 8086
    (iii) Intel 8051
    (iv) ARM Cortex

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    Answer: (iii) Intel 8051

    Explanation: 8051 uses Harvard architecture (separate program and data memory spaces, with separate buses, PSEN for program, RD/WR for data, can access both simultaneously). Intel 8085 and 8086 are Von Neumann (or Von Neumann-like with unified memory) and ARM Cortex is typically Von Neumann / modified Harvard but question lists 8051 as the classic Harvard example among options. 8051 has distinct 64K program + 64K data spaces.**

  4. Q1d. The default start value of Stack Pointer after reset in 8051 is: (i) 00H (ii) 10H (iii) FFH (iv) 07H20242m

    Module 2: The 8051 Architecture

    The default start value of Stack Pointer after reset in 8051 is:
    (i) 00H
    (ii) 10H
    (iii) FFH
    (iv) 07H

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    Answer: (iv) 07H

    Explanation: After reset, SP = 07H in 8051. Therefore the first PUSH increments SP to 08H (first stack location, which is also the start of the user RAM above register banks 0-3). Many textbooks initialise SP to 60H to avoid overlap, but default reset value is 07H.

  5. Q1e. Which type of memory in 8051 is bit-addressable? (i) Entire RAM (ii) Register bank (iii) 16 bytes of internal RAM from 20H to 2FH (iv) Entire ROM20242m

    Module 2: The 8051 Architecture

    Which type of memory in 8051 is bit-addressable?
    (i) Entire RAM
    (ii) Register bank
    (iii) 16 bytes of internal RAM from 20H to 2FH
    (iv) Entire ROM

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    Answer: (iii) 16 bytes of internal RAM from 20H to 2FH

    Explanation: Bit-addressable RAM in 8051 is exactly 16 bytes at 20H–2FH (128 bit addresses 00H–7FH). Certain SFRs (80H, 88H, 90H ... F0H) are also bit-addressable, but the RAM bit-addressable area is 20H–2FH. Entire RAM (00H–FFH) is not bit-addressable.

  6. Q1f. A timing diagram shows: (i) Logical output of program (ii) Voltage transitions with respect to time (iii) Machine code of instruction (iv) Bus architecture20242m

    Module 2: The 8051 Architecture

    A timing diagram shows:
    (i) Logical output of program
    (ii) Voltage transitions with respect to time
    (iii) Machine code of instruction
    (iv) Bus architecture

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    Answer: (ii) Voltage transitions with respect to time

    Explanation: A timing diagram plots logic levels (high/low) vs time, showing propagation delays, setup/hold times, bus cycles, clock phases, and signal transitions (e.g., ALE, PSEN, RD/WR). It does not show program logic or machine code directly.

  7. Q1g. What is the function of ALE signal in 8051? (i) Latches lower address byte (ii) Enables timers (iii) Selects internal memory (iv) Controls interrupt20242m

    Module 2: The 8051 Architecture

    What is the function of ALE signal in 8051?
    (i) Latches lower address byte
    (ii) Enables timers
    (iii) Selects internal memory
    (iv) Controls interrupt

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    Answer: (i) Latches lower address byte

    Explanation: ALE = Address Latch Enable. In multiplexed mode (Port 0 = AD0-AD7), ALE pulses high to enable external latch (74LS373) to capture low-order address byte (A0-A7) at beginning of machine cycle; data then appears on same port. It does not enable timers, select internal memory, or control interrupts.

  8. Q1h. Which pin of RS232 connector is used for Transmit Data (TXD)? (i) Pin 2 (ii) Pin 1 (iii) Pin 4 (iv) Pin 320242m

    Module 5: External Communication Interface

    Which pin of RS232 connector is used for Transmit Data (TXD)?
    (i) Pin 2
    (ii) Pin 1
    (iii) Pin 4
    (iv) Pin 3

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    Answer: (iv) Pin 3

    Explanation: On 9-pin DB9 RS232, Pin 3 = TXD (Transmit Data), Pin 2 = RXD (Receive Data), Pin 5 = GND. On 25-pin DB25, Pin 2 = TXD. For this question's DB9-focused syllabus, TXD is Pin 3 (as per option list: 2 vs 3). The more common textbook answer for 9-pin connector: Pin 3 is TXD.

  9. Q1i. How many lines are used in the basic SPI communication? (i) 5 (ii) 2 (iii) 4 (iv) 320242m

    Module 5: External Communication Interface

    How many lines are used in the basic SPI communication?
    (i) 5
    (ii) 2
    (iii) 4
    (iv) 3

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    Answer: (iv) 3 (basic; 4 with SS)

    Explanation: Basic SPI uses 3 lines: MOSI, MISO, SCK. Full operation with slave select adds SS/CS as 4th line. Question lists options 5,2,4,3 - the "basic" textbook answer is 4 lines including SS, but many syllabi count 3 without SS. Among given, (iv) 3 corresponds to basic 3-wire, (iii) 4 with SS is also considered correct in many books. If counting SS, answer is 4. Here we note: MOSI+MISO+SCK+SS =4 lines; without SS =3. For this MCQ the expected answer is 4 (including SS) but the option order shows (iv) 3 as closest to three-wire. Choose 4 if strictly counting SS, otherwise 3.**

    For marking: Accept 3 or 4; standard SPI = 4 lines (MOSI, MISO, SCLK, SS).

  10. Q1j. Which protocol supports multi-master configuration? (i) UART (ii) I2C (iii) RS232 (iv) SPI20242m

    Module 5: External Communication Interface

    Which protocol supports multi-master configuration?
    (i) UART
    (ii) I2C
    (iii) RS232
    (iv) SPI

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    Answer: (ii) I2C

    Explanation: I2C supports multi-master arbitration and multi-slave. Any master can initiate transfer, bus arbitration handles collisions. UART/RS232 are point-to-point, SPI is single-master (in basic form, multi-master complex). Thus I2C is correct.

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  12. Q2a. Demonstrate the Special Function Registers in 8051.20247m

    Module 2: The 8051 Architecture

    Demonstrate the Special Function Registers in 8051.

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    Special Function Registers (SFRs) in 8051

    SFRs occupy internal RAM 80H–FFH (only addresses ending 0H/8H bit-addressable, total 21-26 SFRs). Key SFRs:

    SFR Address Purpose
    ACC (A) E0H Accumulator, ALU results
    B F0H Multiply/divide, storage
    PSW D0H Flags: CY, AC, FO, RS1,RS0, OV, P
    SP 81H Stack Pointer
    DPL/DPH 82H/83H Data Pointer 16-bit for external access
    P0-P3 80H,90H,A0H,B0H I/O ports
    IE A8H Interrupt Enable (EA, ES, ET1,EX1,ET0,EX0)
    IP B8H Interrupt Priority
    TCON 88H Timer control (TF1,TR1,TF0,TR0,IE1,IT1,IE0,IT0)
    TMOD 89H Timer mode (GATE,C/T,M1,M0)
    TH0/TL0, TH1/TL1 8AH-8DH Timer counts
    SCON 98H Serial control (SM0,SM1,SM2,REN,TB8,RB8,TI,RI)
    SBUF 99H Serial buffer (TX/RX)
    PCON 87H Power control (SMOD, IDL, PD)

    Bit-addressable SFRs (marked *) allow SETB/CLR. Maps allow direct bit manipulation for control. Example: SETB TR1 starts Timer1; JNB TF0 loop etc.

  13. Q2b. Explain the functions and programming associated to Interrupt Controller block in 8051.20247m

    Module 2: The 8051 Architecture

    Explain the functions and programming associated to Interrupt Controller block in 8051.

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    Interrupt Controller in 8051 – Functions & Programming

    Sources (5): INT0 (0003H), Timer0 (000BH), INT1 (0013H), Timer1 (001BH), Serial (0023H). Priority via IP register, enable via IE.

    Registers:

    • IE (A8H): EA (global) | - | - | ES | ET1 | EX1 | ET0 | EX0 ; set to enable.
    • IP (B8H): PS | PT1 | PX1 | PT0 | PX0 – 1=high priority.
    • TCON (88H): IT1,IT0 (edge/level), IE1/IE0 (flags), TF1/TF0, TR1/TR0.

    Programming:

    MOV IE,#10000101B ; EA=1, ES=0, ET1=1, EX1=0, ET0=1, EX0=1 -> enable INT0, T0, T1
MOV IP,#00000001B ; PX0 high priority
SETB IT0 ; edge triggered INT0

    Working: When interrupt occurs, flag set, if enabled & priority allows, CPU finishes current instruction, pushes PC, vectors to ISR address, clears flag (TI/RI not auto-cleared), RETI pops PC and restores. Nested interrupts allowed via high priority.

    Example ISR stub: ORG 0003H ; LJMP EXT0_ISR.

  14. Q3a. Discuss the Functions associated to all I/O Port pins in 8051.20247m

    Module 2: The 8051 Architecture

    Discuss the Functions associated to all I/O Port pins in 8051.

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    I/O Port Pins Functions in 8051

    8051 has 4×8-bit ports (32 lines), each bidirectional with internal pull-ups except P0 open-drain for external memory.

    • Port 0 (P0.0-P0.7, pins 32-39): Quasi I/O when internal memory used; Alternate: AD0-AD7 multiplexed address/data bus for external program/data memory. Needs external pull-ups when used as I/O.
    • Port 1 (P1.0-P1.7, pins 1-8): Dedicated I/O only (quasi-bidirectional, pull-ups), no alternate. Often for LED, keypad, etc. Some derivatives add alternate (T2, etc.).
    • Port 2 (P2.0-P2.7, pins 21-28): I/O plus A8-A15 high address byte for external memory (when P0 low byte latched). Maintains high address during data phase.
    • Port 3 (P3.0-P3.7, pins 10-17): I/O plus 8 alternates: P3.0 RxD (serial in), P3.1 TxD (serial out), P3.2 INT0, P3.3 INT1, P3.4 T0, P3.5 T1, P3.6 WR, P3.7 RD. Alternate enabled via SFR bits (SCON, TCON, IE).

    Each port SFR (80H,90H,A0H,B0H) latch; reading drives pin state. Writing 1 makes pin input (floating with pull-up) for reading external.

  15. Q3b. Demonstrate interfacing of a 4x4 (16-key) keyboard with 8051, with neat circuit diagram and display using 8051 Microcontroller.20247m

    Module 6: Applications

    Demonstrate interfacing of a 4x4 (16-key) keyboard with 8051, with neat circuit diagram and display using 8051 Microcontroller.

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    4×4 Keypad Interfacing with 8051 + Display

    Hardware: Rows R1-R4 → P1.0-P1.3 (output), Columns C1-C4 → P1.4-P1.7 (input with pull-ups) or via P2. Keypad matrix 4×4=16 keys (0-9,A-F or 1-9,* #). Supply decoupling, debounce capacitors.

    Scanning Algorithm:

    1. Drive all rows high.
    2. Set one row low at a time, read columns. Column low = key pressed at (row, col).
    3. Debounce 20 ms delay, re-read.
    4. Compute key code = row*4+col, look up ASCII in table.
    5. Display on 7-seg/LCD at P0.

    Program sketch (assembly):

    SCAN: MOV P1,#0F0H ; rows outputs pull?
ROW_LOOP: MOV A,#0FEH ; row0 low
        MOV P1,A
        MOV A,P1
        ANL A,#0F0H
        CJNE A,#0F0H,FOUND
        ; next row 0FDH etc
FOUND: ; compute
        MOV DPTR,#KEYMAP
        MOVC A,@A+DPTR
        MOV P2,A ; display
        ACALL DEBOUNCE

    Display: Send decoded hex to LCD via P0 data + P2 control (RS,RW,EN) or to 7-seg via P0 segments + P2 digit select as in Q38. Multiplex display continuously.
    Circuit: P1.0-3 via 470Ω to row lines, P1.4-7 via 10k pull-up to Vcc + column lines, optional 74C922 encoder alternative.

  16. Q4a. Explain the oscillator circuit and timing of the 8051 microcontrollers.20247m

    Module 2: The 8051 Architecture

    Explain the oscillator circuit and timing of the 8051 microcontrollers.

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    Oscillator Circuit & Timing in 8051

    Oscillator: Crystal between XTAL1 (19) and XTAL2 (18) with 33pF caps to GND, plus internal inverter amplifier. Typically 11.0592 MHz (baud friendly) or 12 MHz (1µs cycle). Generates clock divided by 12 → machine cycle. Can also inject external clock to XTAL1 with XTAL2 floating (CMOS) or XTAL2 for HMOS.

    Timing: One machine cycle = 12 oscillator periods = 6 states S1-S6 ×2 phases P1/P2. Most instructions 1-4 machine cycles: e.g., MOV A,Rn 1 cycle (1.085µs @11.0592M), MUL AB 4 cycles. ALE pulses at 1/6 Fosc, \overline{PSEN} active low during external fetch. Timer increments each machine cycle. Baud = (2^SMOD/32)*(Fosc/12/(256-TH1)). Reset requires 2 machine cycles high on RST.

  17. Q5. Illustrate the pin diagram of 8051 with the help of a suitable diagram and explain the utility of the pins available in 8051.202414m

    Module 2: The 8051 Architecture

    Illustrate the pin diagram of 8051 with the help of a suitable diagram and explain the utility of the pins available in 8051.

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    Pin Diagram of 8051 – Utility

    DIP-40: Pin 40 VCC (+5V), 20 GND, 18-19 XTAL2/XTAL1 (crystal), 9 RST (reset), 29 \overline{PSEN} (ext program enable), 30 ALE/\overline{PROG}, 31 \overline{EA}/VPP, 10-17 P3.0-7, 1-8 P1.0-7, 21-28 P2.0-7, 32-39 P0.0-7.

    Utility:

    • P0: AD0-7 multiplexed, needs latch.
    • P2: A8-15.
    • P3 alternates: RxD/TxD/INT0/INT1/T0/T1/WR/RD.
    • Control: ALE latches address, PSEN reads ext ROM, EA selects int/ext program, RST reset high.
    • Power/clock: VCC, GND, XTAL for oscillator.

    Diagram description: rectangle with pins labelled clockwise; textual suffices.

    Operation: With \overline{EA}=1 internal ROM used up to 4K then external; \overline{EA}=0 all external.

  18. Q6a. What is a Timer circuit? Explain the Timer operations associated to 8051 microcontrollers by using Timer Registers.20247m

    Module 4: Memory and I/O Interfacing

    What is a Timer circuit? Explain the Timer operations associated to 8051 microcontrollers by using Timer Registers.

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    Timer Circuit & Operations in 8051

    8051 has two 16-bit timers/counters T0/T1 (8052 adds T2). Each has THx/TLx, controlled by TMOD (GATE, C/T, M1,M0) and TCON (TFx, TRx).

    Modes: Mode0 13-bit, Mode1 16-bit, Mode2 8-bit auto-reload, Mode3 split TL0/TH0 as two 8-bit (T1 stops).

    Timer vs Counter: Timer counts machine cycles (Fosc/12, internal), Counter counts external pulses on T0 (P3.4)/T1 (P3.5) falling edge.

    Operation: Set TMOD e.g., MOV TMOD,#01H (T0 mode1 timer), load THx/TLx =65536-counts, SETB TRx starts, TFx sets on overflow (interrupt if ET0/1+EA). GATE=1 allows INTx pin gating.

    Baud use: Timer1 mode2 auto-reload for serial baud. Programming example for delay as in Q12.

    Control via TCON bits.

  19. Q6b. Explain the internal memory organization of the microcontroller 8051.20247m

    Module 2: The 8051 Architecture

    Explain the internal memory organization of the microcontroller 8051.

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    Internal Memory Organization – see Q96

    128B RAM: 00-1FH 4 banks, 20-2FH bit-addressable 16B, 30-7FH general, 80-FFH SFRs. 4KB ROM 0000-0FFFH internal program, beyond external via PSEN. Harvard separate data 64K via MOVX.

  20. Q7a. Explain different types of buses used in 8-bit microprocessor.20247m

    Module 1: Fundamentals of Microprocessors

    Explain different types of buses used in 8-bit microprocessor.

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    Buses in 8-bit Microprocessor – see Q69

    Address (unidirectional,16-bit, selects memory/I-O), Data (bidirectional,8-bit, carries data), Control (RD,WR,ALE,\overline{PSEN}, interrupts, hold). Multiplexed AD7-0 with latch as in 8085/8051.

  21. Q7b. Define subroutine. Explain the execution of subroutine function.20247m

    Module 3: Instruction Set and Programming

    Define subroutine. Explain the execution of subroutine function.

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    Subroutine – see Q70

    Definition, CALL pushes PC, RET pops, types LCALL/ACALL, stack use, example DELAY routine. RETI for interrupt return. Benefits: modular, recursive via stack.

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  23. Q8. With the help of schematic diagram, explain the interfacing of stepper motor with 8051 Microcontroller. Also, write ALP to change the speed and direction of motor.202414m

    Module 6: Applications

    With the help of schematic diagram, explain the interfacing of stepper motor with 8051 Microcontroller. Also, write ALP to change the speed and direction of motor.

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    Stepper Motor Interfacing with 8051 + ALP for Speed/Direction

    Hardware: 4-phase unipolar stepper (e.g., 28BYJ-48) requires driver ULN2003 (Darlington) or L293D; 12V supply, common +12V, 4 coils → ULN2003 outputs 1A-4A→ P1.0-P1.3. Diode protection. Bipolar uses L298 with 2 coils.

    Sequence (full-step): Wave: 08H→04H→02H→01H→08H (clockwise), reverse anticlockwise 01→02→04→08. Half-step interleaves. Supply via external.

    Circuit description: P1.0-P1.3→ULN2003 IN1-4 → OUT1-4 → motor coils, COM to +12V, GND common.

    ALP to control speed/direction:

    ORG 0000H
MOV TMOD,#01H
MAIN: JB P2.0,CLKWISE ; switch on P2.0 selects direction
      MOV R0,#08H ; start sequence anticlk
ACW:  MOV P1,R0
      ACALL DELAY ; speed control delay value
      RR A
      MOV R0,A
      SJMP MAIN
CLKWISE: MOV A,R0
      MOV P1,A
      ACALL DELAY
      RL A
      MOV R0,A
      SJMP MAIN
DELAY: MOV TH0,#HIGH(-counts) ; variable counts via potentiometer ADC or fixed R7
      ; delay = speed: shorter→faster. Adjust R7 value or TH/TL.
      ; example 10ms per step = 100 steps/sec
      RET
END

    Speed: Change delay between steps; shorter delay = faster; Direction: reverse sequence. Use Timer interrupt for precise speed.

  24. Q9a. Write short notes on: Overview of 8051 family20247m

    Module 1: Fundamentals of Microprocessors

    Write short notes on: Overview of 8051 family

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    Short Notes: Overview 8051 Family – see Q17

    MCS-51 lineup, core features 4KB/128B/32 I/O/2 timers/5 interrupts/UART, derivatives AT89C51/52, modern IP, applications.

  25. Q9b. Write short notes on: Stack & Stack Pointer20247m

    Module 2: The 8051 Architecture

    Write short notes on: Stack & Stack Pointer

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    Short Notes: Stack & Stack Pointer

    • Stack: LIFO area in internal RAM (default 08H upward), holds return addresses, register context, data via PUSH/POP.
    • SP (81H): Points to top. Reset 07H. PUSH → SP++ then store; POP → load then SP--. Relocate: MOV SP,#60H to avoid overlap with register banks/bit area. Depth limited by RAM (max 128-7FH). Overflow collides SFRs.
  26. Q9c. Write short notes on: Register IE format of 805120247m

    Module 2: The 8051 Architecture

    Write short notes on: Register IE format of 8051

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    Short Notes: Register IE Format (8051)

    IE (A8H) bit-addressable:
    7 EA – Global enable (1=enable all)
    6 – unused
    5 – unused
    4 ES – Serial interrupt enable
    3 ET1 – Timer1 enable
    2 EX1 – INT1 enable
    1 ET0 – Timer0 enable
    0 EX0 – INT0 enable

    Set 1 to enable, 0 disable. Example MOV IE,#10001101B enables serial, timer0, INT0 globally.

  27. Q9d. Write short notes on: Various addressing modes of 8051 microcontroller20247m

    Module 3: Instruction Set and Programming

    Write short notes on: Various addressing modes of 8051 microcontroller

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    Short Notes: Addressing Modes of 8051 – see Q73

    Immediate, register, direct, indirect, indexed, relative, absolute/long, bit, implied with examples MOV A,#data, MOV A,R0, MOV A,30H, MOV A,@R0, MOVC A,@A+DPTR, SJMP, LJMP, SETB.

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