2023 question paper

MICROPROCESSORS

27 questions

Q1a. For 16-bit operations, register E can be paired with what register? (i) A (ii) B (iii) C (iv) D20232m
Module 1: Fundamentals of Microprocessors
For 16-bit operations, register E can be paired with what register?
(i) A
(ii) B
(iii) C
(iv) D

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Worked Solution
Answer: (iv) D

Explanation: In 8085 (and 8086-compatible 8-bit register pairing for 16-bit operations), the general-purpose registers are paired as:

B-C → B is high byte, C low byte

D-E → D is high byte, E low byte

H-L → H is high byte, L low byte

For 16-bit data operations (LXI, DAD, STAX/LDAX, LHLD/SHLD using H-L), E must be paired with D to form the 16-bit register pair D-E. Similarly in some textbooks "E can be paired with D" for 16-bit moves. Option (iv) D is correct.
Q1b. Which of the following control signal becomes high in T1 clock cycle and remains deactivated in T2 clock cycle and onwards? (i) ALE (ii) \overline{PSEN} (iii) \overline{EA} (iv) All of the above20232m
Module 1: Fundamentals of Microprocessors
Which of the following control signal becomes high in T1 clock cycle and remains deactivated in T2 clock cycle and onwards?
(i) ALE
(ii) $\overline{PSEN}$
(iii) $\overline{EA}$
(iv) All of the above

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Worked Solution
Answer: (i) ALE

Explanation: ALE (Address Latch Enable) is the 8051 output that pulses high during state T1 of each machine cycle to latch the low-byte address (P0) into an external latch (74LS373). It then goes low and remains low (deactivated) during T2 and onwards for that cycle, while \overline{PSEN} (active-low) goes low during the fetch phase. \overline{EA} is an input. So the signal that becomes high in T1 and stays deactivated thereafter is ALE.
Q1c. JP instruction in 8085 performs branch if: (i) Carry flag is 1 (ii) Parity flag is 1 (iii) Sign flag is 0 (iv) Auxiliary carry flag is 020232m
Module 3: Instruction Set and Programming
JP instruction in 8085 performs branch if:
(i) Carry flag is 1
(ii) Parity flag is 1
(iii) Sign flag is 0
(iv) Auxiliary carry flag is 0

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Worked Solution
Answer: (iii) Sign flag is 0

Explanation: In 8085, JP = Jump if Plus (positive) - branches when Sign flag S = 0 (result positive, MSB =0). JM jumps if S=1 (minus). JZ/JNZ test Zero, JC/JNC test Carry, JP/JM test Sign, JPE/JPO test Parity. JP specifically: if S=0 then PC←address. So option (iii) Sign flag 0.
Q1d. The instruction to copy the content of a memory location using a register indirect addressing mode is? (i) STAX (ii) LDAX (iii) LDA (iv) None of the above20232m
Module 3: Instruction Set and Programming
The instruction to copy the content of a memory location using a register indirect addressing mode is?
(i) STAX
(ii) LDAX
(iii) LDA
(iv) None of the above

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Worked Solution
Answer: (ii) LDAX

Explanation: In 8085, LDAX B/D (Load Accumulator indirect) copies content of memory location whose 16-bit address is in register pair B-C or D-E into accumulator using register-indirect addressing. STAX does the opposite (A → memory). LDA is direct 16-bit address. Hence LDAX uses register indirect.
Q1e. Which of the following statement is true for the instruction PUSH B? (i) It is an arithmetic instruction (ii) Executes in single machine cycle (iii) It reads from memory location (iv) It performs memory write operation20232m
Module 3: Instruction Set and Programming
Which of the following statement is true for the instruction PUSH B?
(i) It is an arithmetic instruction
(ii) Executes in single machine cycle
(iii) It reads from memory location
(iv) It performs memory write operation

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Worked Solution
Answer: (iv) It performs memory write operation

Explanation: PUSH B (push register B onto stack) increments SP then writes B to internal RAM at [SP]. So it is a memory write, not read, not arithmetic. It takes 2 machine cycles (24 oscillator periods) on 8051, not single. It uses direct addressing for B but stack operation is indirect via SP. Hence only (iv) is true.
Q1f. The number of pins in 8051 microcontroller is? (i) 64 (ii) 44 (iii) 40 (iv) 10020232m
Module 2: The 8051 Architecture
The number of pins in 8051 microcontroller is?
(i) 64
(ii) 44
(iii) 40
(iv) 100

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Worked Solution
Answer: (iii) 40

Explanation: Standard 8051 (DIP-40) has 40 pins: 32 I/O (P0-P3), 2 crystal (XTAL1/2), RST, EA/VPP, ALE/PROG, PSEN, VCC, VSS. Other packages (PLCC-44, TQFP-44 with 44 pins) exist, but classic 8051 is 40-pin DIP.
Q1g. The value of RAM is to ROM size ratio is lower in? (i) Microprocessor based systems (ii) Microcontroller based systems (iii) Both (i) and (ii) (iv) None of the above20232m
Module 1: Fundamentals of Microprocessors
The value of RAM is to ROM size ratio is lower in?
(i) Microprocessor based systems
(ii) Microcontroller based systems
(iii) Both (i) and (ii)
(iv) None of the above

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Worked Solution
Answer: (ii) Microcontroller based systems

Explanation: Microcontrollers are single-chip systems with on-chip ROM + RAM + I/O optimized for control tasks, so they need small RAM relative to ROM (code heavy). Microprocessor-based systems use large external RAM for general computing. Hence RAM:ROM ratio is lower in microcontroller-based systems.
Q1h. The number of hardware interrupts in 8051 is? (i) 2 (ii) 3 (iii) 4 (iv) 520232m
Module 2: The 8051 Architecture
The number of hardware interrupts in 8051 is?
(i) 2
(ii) 3
(iii) 4
(iv) 5

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Worked Solution
Answer: (iv) 5

Explanation: 8051 has 5 interrupt sources (interrupt vector addresses):

INT0 (0003H) external

Timer 0 overflow TF0 (000BH)

INT1 (0013H) external

Timer 1 overflow TF1 (001BH)

Serial RI+TI (0023H)
Some derivatives add extra, but classic 8051 has 5; 2 are external hardware interrupts.
Q1i. Which member of MCS-51 family contains an internal ROM of 0 KB? (i) 8051 (ii) 8951 (iii) 8031 (iv) None of the above20232m
Module 1: Fundamentals of Microprocessors
Which member of MCS-51 family contains an internal ROM of 0 KB?
(i) 8051
(ii) 8951
(iii) 8031
(iv) None of the above

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Worked Solution
Answer: (iii) 8031

Explanation: MCS-51 family: 8051 = 4KB ROM, 8052 = 8KB, 8031 = 0KB internal ROM (ROMless version requiring external program memory,
EA\ must be grounded). 8751 = EPROM, 8951/AT89C51 = Flash. Hence 8031 has 0KB internal ROM.
Q1j. Which of the following statement is false regarding the RTS and CTS signals? (i) RTS is on the receiver side (ii) CTS is on the transmitter side (iii) RTS is made low at first (iv) CTS is made low at first20232m
Module 5: External Communication Interface
Which of the following statement is false regarding the RTS and CTS signals?
(i) RTS is on the receiver side
(ii) CTS is on the transmitter side
(iii) RTS is made low at first
(iv) CTS is made low at first

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Worked Solution
Answer: (iv) CTS is made low at first (false statement)

Explanation: In RTS/CTS handshake, RTS (Request To Send) is asserted low first by the transmitter/receiver requesting to send, then the other side asserts CTS (Clear To Send) low to grant permission. Saying "CTS is made low at first" reverses the sequence, so it is the false statement. RTS originates at DTE, CTS is response.
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Q2a. What is an embedded system? Describe the salient features and characteristics of an embedded system.20237m
Module 1: Fundamentals of Microprocessors
What is an embedded system? Describe the salient features and characteristics of an embedded system.

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Worked Solution
Embedded System – Salient Features & Characteristics

Definition: Embedded system is a dedicated computer + software hidden inside a product to perform specific control/monitoring.

Salient Features:

Single/defined function - optimized for one task.

Real-time operation - must respond within deadlines (hard/soft real-time).

Resource constrained - limited memory, CPU, power.

Reliability & stability - long uptime without failure.

Low cost, small size, low power - mass-produced.

Hardware-Software co-design - tightly coupled.

Interactive & reactive - responds to sensors/environment.

Microcontroller/SoC based - integrates CPU, memory, I/O on chip.

Characteristics:

Application specific, firmware in ROM/Flash.

Minimal UI or headless.

Uses cross-development tools.

Often has no or small OS (RTOS).

Must tolerate temperature, EMI as per deployment.

Examples differentiate from general-purpose computer which is programmable for many tasks.
Q2b. How does an MCS-51 family microcontrollers find use in embedded systems?20237m
Module 1: Fundamentals of Microprocessors
How does an MCS-51 family microcontrollers find use in embedded systems?

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Worked Solution
MCS-51 in Embedded Systems

MCS-51 (8051) is ideal for small embedded control because:

Single-chip: 4KB ROM, 128B RAM, 32 I/O, 2 timers, UART, interrupts on chip → minimal external hardware.

Bit addressability & Boolean processor → efficient control logic.

Real-time: Timer/counter, external interrupts INT0/1, serial for communication.

Low cost & power, mature tools: Keil C, many derivatives (Atmel, NXP), wide industrial support.

Interfacing: Direct to sensors (ADC), LCD, keypad, stepper/motor,7-seg, I2C/SPI bridges.
Use cases: washing machine, traffic controller, medical pump, automotive, industrial automation. Limited for high-performance (use ARM for 32-bit), but still dominates 8-bit control.
Q3a. Explain how the address and data information is separated on the address data pins of 8085 microprocessor during the instruction fetch and execution stages.20237m
Module 1: Fundamentals of Microprocessors
Explain how the address and data information is separated on the address data pins of 8085 microprocessor during the instruction fetch and execution stages.

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Worked Solution
Address/Data Separation on 8085

8085 has multiplexed AD7-AD0 (low address + data) to save pins.

Mechanism:

T1 of machine cycle: ALE (Address Latch Enable) high → AD7-AD0 carries A7-A0. External latch (74LS373) captures it when ALE falls. A15-A8 already stable on high bus.

T2-T3: ALE low → AD7-AD0 now becomes D7-D0 bidirectional data bus for read/write. Control signals IO/M, RD, WR determine direction.

Demultiplexing: ALE→LE of 74LS373 latches address; after that data flows.

Thus address and data share pins time-multiplexed, separated by ALE timing, enabling 16-bit address with 8-bit data on 40-pin package. Equivalent in 8051 Port0 behaves similarly.
Q3b. What are the different program development tools used in microprocessor and microcontrollers?20237m
Module 3: Instruction Set and Programming
What are the different program development tools used in microprocessor and microcontrollers?

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Worked Solution
Program Development Tools (Microprocessor/Microcontroller)

Editor/IDE: Keil µVision, MPLAB, Arduino IDE.

Assembler: Converts mnemonics→machine code (e.g., ASM51).

Cross-Compiler: C/C++→hex (Keil C51, GCC).

Linker/Locator: Combines objects, assigns addresses.

Simulator: Software simulation without hardware.

Emulator/ICE: Hardware replacement for real-time debug.

Debugger: Breakpoints, step, register view.

Programmer/Flash loader: ISP, boot-loader, USB programmers.

Logic Analyzer, Oscilloscope, Burner.
Q4a. What are the different addressing modes used in microprocessor? Explain with suitable instruction examples.20237m
Module 3: Instruction Set and Programming
What are the different addressing modes used in microprocessor? Explain with suitable instruction examples.

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Worked Solution
Addressing Modes in Microprocessor (8051/8085) with Examples

Immediate: Data in instruction. MOV A,#25H, MVI A,30H

Register: Operands in registers. MOV A,R0, ADD A,R1, MOV A,B

Direct: 8-bit direct address. MOV A,30H (internal RAM/SFR), STA 2500H

Register Indirect: Address in register pair. MOV A,@R0, LDAX B, MOVX A,@DPTR

Indirect (via memory pointer): MOV A,@A+DPTR (indexed)

Indexed: Base+index e.g., MOVC A,@A+DPTR, MOVC A,@A+PC

Relative: PC+offset SJMP -10H, JC LOOP

Absolute: 11/16-bit address LJMP 1000H, AJMP LOOP

Bit: Bit addressable SETB P1.0, CLR 20H.3

Implied: NOP, CPL A

Each mode defines how effective address/data is fetched.
Q4b. What are the different instruction types supported in 8085 microprocessor? Explain with suitable instruction examples.20237m
Module 3: Instruction Set and Programming
What are the different instruction types supported in 8085 microprocessor? Explain with suitable instruction examples.

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Worked Solution
Instruction Types in 8085

Data Transfer: MOV, MVI, LXI, LDA, STA, LHLD, SHLD, LDAX, STAX, XCHG, PUSH, POP, IN, OUT. E.g., MOV A,B copy B→A, LXI H,2500H load pointer.

Arithmetic: ADD, ADC, SUB, SBB, INR, DCR, INX, DCX, DAD, DAA. E.g., ADD B A←A+B.

Logical: ANA, ORA, XRA, CMP, CMA, RAL, RAR, ANI. E.g., ANA B A←A & B.

Branching: JMP, JC, JZ, CALL, RET, RST, PCHL. JNZ 2000H

Machine Control: NOP, HLT, DI, EI, SIM, RIM.

Each type corresponds to operation performed on data/address/control flow.
Q5a. Describe the memory organization in 8051 microcontroller.20237m
Module 2: The 8051 Architecture
Describe the memory organization in 8051 microcontroller.

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Worked Solution
Memory Organization in 8051

Separate Harvard spaces: Program (64K, \overline{PSEN}) and Data (64K, \overline{RD}/\overline{WR}), plus Internal Data.

Internal Data (256B):

00H-1FH: 4 register banks (R0-R7) selectable by RS1,RS0 in PSW.

20H-2FH: 16 bytes bit-addressable (128 bits).

30H-7FH: General purpose RAM.

80H-FFH: SFRs (only direct addressing; 80H,88H...F0H bit-addressable).

External: Up to 64K program ROM (via \overline{PSEN}+ALE latch) and 64K data RAM (MOVX). \overline{EA}=0 forces external program from 0000H; =1 uses internal 0000-0FFFH then external beyond.

Access: MOV for internal direct/indirect, MOVX for external data, MOVC for program table.
Q5b. Explain the functions of SP and PC registers in 8051 microcontroller.20237m
Module 2: The 8051 Architecture
Explain the functions of SP and PC registers in 8051 microcontroller.

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Worked Solution
Functions of SP and PC

Stack Pointer (SP, 81H, 8-bit): Points to top of stack in internal RAM. PUSH increments then writes, POP reads then decrements. SP=07H after reset → first push to 08H. Manages calls, interrupts, context save. Can relocate: MOV SP,#60H.

Program Counter (PC, 16-bit): Holds address of next instruction byte. Automatically increments on fetch; loaded by LJMP/AJMP/SJMP/CALL/RET/interrupt vectoring. Determines execution flow. Invisible directly but accessed via MOVC, PUSH PC via CALL.

Together they control sequence (PC) and LIFO storage (SP) for subroutines/interrupts.
Q6a. Write a C or assembly language program for 8051 microcontroller to create a travelling light pattern connected at port 0 after every 500 ms. Assume there are 8 LEDs connected to 8 pins of port 0. Initially after startup, the LED connected to Pin 0 should be ON. Then after 500 ms, the next LED should be ON. Only one LED should be ON at a time and remaining should stay OFF. Continue this pattern forever. Assume the crystal frequency to be 12 MHz.20237m
Module 6: Applications
Write a C or assembly language program for 8051 microcontroller to create a travelling light pattern connected at port 0 after every 500 ms. Assume there are 8 LEDs connected to 8 pins of port 0. Initially after startup, the LED connected to Pin 0 should be ON. Then after 500 ms, the next LED should be ON. Only one LED should be ON at a time and remaining should stay OFF. Continue this pattern forever. Assume the crystal frequency to be 12 MHz.

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Worked Solution
Travelling Light Pattern on Port 0 – 500 ms delay 12MHz

One LED ON at a time moving left→right. Fosc 12MHz → Tcy=1µs, 500ms = 500000 counts = ~7×65536 so use loop with timer + software.

ORG 0000H MOV P0,#01H ; LED0 ON MOV TMOD,#01H LOOP: MOV A,P0 RL A ; rotate left -> next LED MOV P0,A JNB ACC.0,NO_RST ; if wrapped? Actually RL 80H->01H ; delay 500ms ACALL DELAY500 SJMP LOOP DELAY500: ; 500ms via Timer0 loops 50×10ms MOV R7,#50 D500L: MOV TH0,#0DCH ; 10ms =10000 counts → DC00H (12MHz Tcy1us, 65536-10000=55536= D8F0? Need compute; here approximated) MOV TL0,#00H SETB TR0 W: JNB TF0,W CLR TR0 CLR TF0 DJNZ R7,D500L RET END ; Corrected 10ms calc: 10000 decimal=2710H, TH= D8H, TL= F0H for 1us tick

C (more accurate using Timer): Loop 500×1ms interrupts, or use Timer ISR with reload. Principle: load 01H to P0, delay, RL A, write.

Calculation: 12MHz → 1 machine cycle 1µs → Timer mode1 16-bit counts to 65536. 500ms needs 500000 counts → 7 overflows + remainder. Easiest: loop 50 times 10ms delay.
Q6b. Interface 4-digit seven-segment display with 8051 and write a program to display BCD numbers from 0-9 after every 1 second.20237m
Module 6: Applications
Interface 4-digit seven-segment display with 8051 and write a program to display BCD numbers from 0-9 after every 1 second.

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Worked Solution
4-Digit Seven-Segment Display 0-9 Sequence (1 sec) – Hardware as Q38

Use multiplexed P0 segments + P2 digit select.

ORG 0000H MOV TMOD,#01H MAIN: MOV R0,#00H ; digit 0 NEXTDIG: MOV A,R0 MOV DPTR,#SEG MOVC A,@A+DPTR MOV P0,A ; segments MOV A,R0 ; multiplex? Actually display single digit repeated or multiplex all 4 with same? ; For 0-9 counter on all digits, display number as 0000-0009 etc - loop multiplex ACALL DELAY_1S_4DIGITS ; time-share INC R0 CJNE R0,#10,NEXTDIG SJMP MAIN SEG: DB 3FH,06H,5BH,4FH,66H,6DH,7DH,07H,7FH,6FH DELAY_1S: ; via timer outer loop 100×10ms MOV R7,#100 L1: MOV TH0,#0D8H MOV TL0,#0F0H SETB TR0 W: JNB TF0,W CLR TR0 CLR TF0 DJNZ R7,L1 RET

Logic: Increment 0-9, look up cathode code, output to multiplexed display, 1 sec delay using Timer0 counts. For 4-digit, drive same code to all digits simultaneously or BCD increment with carry.
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Q7a. What are the branching instructions in 8051? Explain with suitable examples.20237m
Module 3: Instruction Set and Programming
What are the branching instructions in 8051? Explain with suitable examples.

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Worked Solution
Branching Instructions in 8051

Unconditional jumps: LJMP addr16 (long), AJMP addr11 (absolute page), SJMP rel (short relative).

Conditional jumps: JC rel (if CY=1), JNC, JZ, JNZ, JB bit,rel, JNB, JBC (jump if bit set then clear), DJNZ direct/Reg,rel (decrement & jump not zero), CJNE A,direct,rel / A,#data,rel / Rn,#data,rel / @Ri,#data,rel (compare & jump if not equal).

Calls/Returns: LCALL, ACALL, RET, RETI.

Indirect: JMP @A+DPTR.

Examples:

CJNE A,#10H,NOT_EQ DJNZ R2,LOOP JB P1.0,SET LJMP FAR
Q7b. Explain the following instructions: (i) CJNE (ii) DJNZ20237m
Module 3: Instruction Set and Programming
Explain the following instructions:
(i) CJNE
(ii) DJNZ

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Worked Solution
CJNE & DJNZ Instructions

CJNE (Compare and Jump if Not Equal): Four variants:

CJNE A,direct,rel

CJNE A,#data,rel

CJNE Rn,#data,rel

CJNE @Ri,#data,rel
Operation: CY=1 if first < second, else 0; if not equal, PC←PC+rel else next. Does not store result, only sets CY and jumps. Example:

CJNE A,#10H,NOTEQ ; if A ≠10H jump

Use for compare, sorting.

DJNZ (Decrement & Jump if Not Zero): Two variants: DJNZ direct,rel, DJNZ Rn,rel. Decrement operand, if ≠0 jump. Useful for loops:

MOV R2,#10 LOOP: DJNZ R2,LOOP ; iterate 10 times

Neither affects flags except CY for CJNE; DJNZ affects none except operand.
Q8a. Explain the special function registers associated with the I/O Ports. How to configure an I/O port as an input pin?20237m
Module 2: The 8051 Architecture
Explain the special function registers associated with the I/O Ports. How to configure an I/O port as an input pin?

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Worked Solution
SFRs Associated with I/O Ports & Input Configuration

Port Latches: P0 (80H), P1 (90H), P2 (A0H), P3 (B0H) – each bit latch + driver with pull-up (P0 open-drain).

Input Configuration: 8051 ports are quasi-bidirectional. To configure pin as input:

Write 1 to latch: MOV P1,#0FFH or SETB P1.3 makes FET off, pull-up holds high, external can drive low/high.

Read pin: MOV A,P1 reads pin state (not latch). If alternative function enabled, direction auto.

Example:

MOV P1,#0FFH ; P1 input MOV A,P1 ; read ANL A,#01H JNZ NOT_PRESSED

Alternative functions selected via SFR controls (SCon, TCon etc.) override I/O.
Q8b. What are the special function registers associated with the interrupt module of 8051?20237m
Module 2: The 8051 Architecture
What are the special function registers associated with the interrupt module of 8051?

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Worked Solution
SFRs Associated with Interrupt Module (as Q46/118)

IE A8H (enable bits EA,ES,ET1,EX1,ET0,EX0), IP B8H (priority PS,PT1,PX1,PT0,PX0), TCON 88H (IE1/IT1,IE0/IT0,TF1/TR1,TF0/TR0), SCON 98H (TI/RI). For 8052, additional T2CON etc. Vectors at 0003H-0023H.
Q9a. Write short notes on: Counters20237m
Module 4: Memory and I/O Interfacing
Write short notes on: Counters

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Worked Solution
Short Notes: Counters (8051)

Timers configured as counters when C/T=1 in TMOD count pulses on T0 (P3.4)/T1(P3.5) falling edge.

16-bit count up; overflow TFx→interrupt.

Modes as timers: 13/16/8-bit auto-reload/split.

Used to count external events: pulse counting, frequency measure.

Example: TMOD=06H (T1 counter mode2) counts external.
Q9b. Write short notes on: Interfacing a stepper motor20237m
Module 6: Applications
Write short notes on: Interfacing a stepper motor

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Worked Solution
Short Notes: Interfacing Stepper Motor – see Q128

Unipolar/Bipolar via ULN2003/L293D to P1, sequence 08-04-02-01, speed via delay, direction via sequence reversal. Needs external 12V, diode protection.
Q9c. Write short notes on: Memory Interfacing20237m
Module 4: Memory and I/O Interfacing
Write short notes on: Memory Interfacing

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Worked Solution
Short Notes: Memory Interfacing – see Q152

Demultiplex P0 via 74LS373 + ALE, P2 high address, decoding via 74LS138, \overline{PSEN}→ROM, \overline{RD}/\overline{WR}→RAM, full vs linear decoding, example 16K ROM 0000-3FFFH +8K RAM etc.

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