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2022 question paper

MICROPROCESSORS

24 questions

  1. Q1a. How many flags does 8085 microprocessor has? (i) 4 (ii) 5 (iii) 6 (iv) 320222m

    Module 1: Fundamentals of Microprocessors

    How many flags does 8085 microprocessor has?
    (i) 4
    (ii) 5
    (iii) 6
    (iv) 3

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    Answer

    Correct Option: (ii) 5

    Explanation

    The 8085 microprocessor has 5 flags in its flag register (also called Status Register or Flag Register):

    Flag Name Symbol Purpose
    S Sign S Set if MSB of result = 1 (negative)
    Z Zero Z Set if result = 0
    AC Auxiliary Carry AC Carry from bit 3 to bit 4 (BCD)
    P Parity P Set if result has even parity
    CY Carry CY Carry out of MSB / Borrow

    Total = 5 flags

    Notes

    • Flag register is 8-bit, but only 5 bits are used (bits 0,1,2,4,6 typically).
    • Bits 3 and 5 are reserved/unused in 8085.
    • 8086 has 9 flags (adds OF, DF, IF, TF).
    • Z80 has 4 flags in F register (S,Z,HC,P/V,N,C).

    Final Answer

    8085 has 5 flags → Option (ii)

  2. Q1b. Total bit addressable area in RAM of 8051 microcontroller is ____? (i) 8 bytes (ii) 4 bytes (iii) 16 bytes (iv) 32 bytes20222m

    Module 2: The 8051 Architecture

    Total bit addressable area in RAM of 8051 microcontroller is ____?
    (i) 8 bytes
    (ii) 4 bytes
    (iii) 16 bytes
    (iv) 32 bytes

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    Answer: (iii) 16 bytes

    Explanation: In 8051 internal RAM (00H–7FH), the region 20H–2FH (16 bytes × 8 bits = 128 bits) is bit-addressable. Bits are addressed as 00H–7FH in bit address space. Additionally, most SFRs with addresses ending in 0H or 8H are bit-addressable, but the question asks about RAM area, which is 16 bytes. Some textbooks note 16 bytes = 128 bits.

  3. Q1d. What can be the oscillator period for the multiplication operation of A and B in accordance to 16-bit product especially in B:A registers? (i) 12 (ii) 24 (iii) 36 (iv) 4820222m

    Module 3: Instruction Set and Programming

    What can be the oscillator period for the multiplication operation of A and B in accordance to 16-bit product especially in B:A registers?
    (i) 12
    (ii) 24
    (iii) 36
    (iv) 48

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    Answer: (iv) 48

    Explanation: Same as Q30 - MUL AB takes 4 machine cycles = 4×12 = 48 oscillator periods (12 clocks per machine cycle on standard 8051). Product placed in B (high byte) : A (low byte). Flags: OV set if product >255, CY cleared.

  4. Q1e. JNC stands for: (i) Jump if no carry, jumps if CY=0 (ii) Jump if carry, jumps if CY=1 (iii) Jump if no carry, jumps if CY=1 (iv) Jump if carry, jumps if CY=020222m

    Module 3: Instruction Set and Programming

    JNC stands for:
    (i) Jump if no carry, jumps if CY=0
    (ii) Jump if carry, jumps if CY=1
    (iii) Jump if no carry, jumps if CY=1
    (iv) Jump if carry, jumps if CY=0

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    Answer: (i) Jump if no carry, jumps if CY=0

    Explanation: JNC = Jump if No Carry. In 8051, JNC rel : if PSW.CY =0 then PC←PC+offset, else next instruction. JC jumps if CY=1. Hence (i) is correct.

  5. Q1f. PUSH and POP instructions are used to ____ and ____ respectively. (i) Send the data from the stack, copy the data to the stack (ii) Send the data to the stack, copy the data from the stack (iii) All of the above (iv) None of the above20222m

    Module 3: Instruction Set and Programming

    PUSH and POP instructions are used to ____ and ____ respectively.
    (i) Send the data from the stack, copy the data to the stack
    (ii) Send the data to the stack, copy the data from the stack
    (iii) All of the above
    (iv) None of the above

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    Answer: (ii) Send the data to the stack, copy the data from the stack

    Explanation: PUSH sends/copies source byte to stack (write, SP++), POP copies data from stack to destination (read, SP--). Option (ii) states PUSH = to stack, POP = from stack, which is correct. Option (i) reverses them.

  6. Q1h. The Abbreviation for ALE is: (i) Address Latch Enable (ii) Address Light External (iii) Address Latch Eternal (iv) None of the above20222m

    Module 2: The 8051 Architecture

    The Abbreviation for ALE is:
    (i) Address Latch Enable
    (ii) Address Light External
    (iii) Address Latch Eternal
    (iv) None of the above

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    Answer: (i) Address Latch Enable

    Explanation: ALE stands for Address Latch Enable - the 8051 output that controls external latch for demultiplexing low address from Port 0.

  7. Q1i. The system program used to translate directly an assembly language to machine language is called: (i) Compiler (ii) Assembler (iii) Text editor (iv) Debugger20222m

    Module 3: Instruction Set and Programming

    The system program used to translate directly an assembly language to machine language is called:
    (i) Compiler
    (ii) Assembler
    (iii) Text editor
    (iv) Debugger

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    Worked Solution

    Answer: (ii) Assembler

    Explanation: Assembler translates assembly mnemonics directly to machine code (opcode + operand). Compiler translates high-level language to machine code, text editor edits source, debugger tests execution.

  8. Q1j. How many interrupts signals exist in 8085? (i) 2 (ii) 3 (iii) 4 (iv) 520222m

    Module 1: Fundamentals of Microprocessors

    How many interrupts signals exist in 8085?
    (i) 2
    (ii) 3
    (iii) 4
    (iv) 5

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    Answer: (iv) 5

    Explanation: 8085 has 5 hardware interrupts in priority order: TRAP (highest, non-maskable), RST 7.5, RST 6.5, RST 5.5, and INTR (lowest). TRAP is vector 0024H, RST 7.5 003CH, 6.5 0034H, 5.5 002CH.

  9. Q2a. What is embedded system? Explain the architecture of an embedded system with neat block diagram.20227m

    Module 1: Fundamentals of Microprocessors

    What is embedded system? Explain the architecture of an embedded system with neat block diagram.

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    Embedded System – Definition & Architecture

    Definition: An embedded system is a computing system designed to perform dedicated functions within a larger mechanical/electrical system, with tight constraints on cost, size, power, and real-time response. It contains a microprocessor/microcontroller, memory, I/O, and firmware.

    Architecture Block Diagram (describe):

    [Sensors/Input]→[Signal Conditioning]→[ADC]→|    Central Unit    |→[DAC/Drivers]→[Actuators/Output]
                                      |  Processor (8051/ARM) |
                                      |  Memory: ROM/Flash,   |
                                      |   RAM, Cache          |
                                      |  Timers/Counters,     |
                                      |  Interrupt Controller |
                                      |  Communication: UART, |
                                      |  SPI, I2C, USB, ETH  |
                                      |  I/O Ports, Power Mgmt|
                                      +-----------+------------+
                                                    |
                                             [Software/Firmware]

    Components:

    1. Processor core: 8051, ARM, AVR, PIC – executes firmware.
    2. Memory: Program Flash/ROM, Data RAM, EEPROM for parameters.
    3. I/O & Peripherals: GPIO, timers, ADC/DAC, PWM, interrupts.
    4. Sensors/Actuators: Input physical signals, output control.
    5. Communication: RS232, I2C, SPI, CAN, USB, Zigbee/BT for connectivity.
    6. Power & Clock: Oscillator, reset, power management.
    7. Software: Real-time OS or bare-metal C/assembly.

    Characteristics: Single function, real-time, resource-constrained, reliable, low cost. Examples: Washing machine, automotive ECU, medical device.

  10. Q2b. Explain the architecture of 8-bit microprocessor.20227m

    Module 1: Fundamentals of Microprocessors

    Explain the architecture of 8-bit microprocessor.

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    Architecture of 8-bit Microprocessor (8085)

    Same as Q143/Q64: Comprises ALU 8-bit, register array (B,C,D,E,H,L, A, FLAGS, PC, SP, temp W,Z), Instruction Register & Decoder, Timing & Control Unit, Interrupt Control, Serial I/O, Address/Data buffers, Oscillator.
    Working cycle: Fetch (M→IR), Decode, Execute (ALU/mem/reg). Bus structure: 16-bit address (A15-A0), 8-bit data (AD7-AD0 multiplexed with ALE), control (RD, WR, IO/M). Stack grows, interrupts vectored. Von Neumann memory. Clocks generate T-states. This compact diagram explains complete operation.

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  12. Q3a. Explain the indexed addressing and relative addressing in 8051 micro-controller.20227m

    Module 3: Instruction Set and Programming

    Explain the indexed addressing and relative addressing in 8051 micro-controller.

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    Indexed & Relative Addressing in 8051

    1. Indexed Addressing: EA = Base + Index. Base is DPTR or PC, index is Accumulator. Instructions: MOVC A,@A+DPTR and MOVC A,@A+PC. Used for table look-up, e.g., fetch byte from code memory table whose base address in DPTR plus offset in A. Example:

    MOV DPTR,#TABLE
MOV A,R2 ; offset 2
MOVC A,@A+DPTR ; A = TABLE[2]
TABLE: DB 10H,20H,30H

    Also MOVX with DPTR indirect is variant.

    2. Relative Addressing: EA = PC + signed 8-bit offset (2's complement, -128 to +127). Used by jumps: SJMP rel, JC/JNC/JZ/JNZ/DJNZ/CJNE rel. Offset relative to next instruction's first byte. Example: SJMP LOOP assembles to -X offset. Allows relocatable code and short jumps within 256-byte range.

  13. Q3b. Explain the various programming and debugging tools in 8051 micro-controller.20227m

    Module 3: Instruction Set and Programming

    Explain the various programming and debugging tools in 8051 micro-controller.

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    Programming & Debugging Tools for 8051

    • Assembler (A51) & Compiler (C51/Keil, SDCC): Translate assembly/C to hex.
    • Simulator (Keil µVision, Proteus): Functional simulation, register/memory view, breakpoints.
    • Emulator (ICE, JTAG): In-circuit emulation with real hardware timing.
    • Programmer/Burner: EPROM/Flash programmer (e.g., TL866) with \overline{EA}/ALE programming mode.
    • Debugger: Single-step, watch windows, trace, logic analyzer, oscilloscope for timers/serial.
    • IDEs: Keil, IAR, Eclipse with 8051 plugin.
    • Development boards: With LEDs, switches, LCD, serial, for testing.
  14. Q4. Show the results of the following: (i) ``assembly MOV A, #35H ANL A, 0FH ` (ii) `assembly MOV A, #04H ORL A, 03H ` (iii) `assembly MOV A, #54H XRL A, A ` (iv) `assembly CLR C MOV A, #26H RRC A ``202214m

    Module 3: Instruction Set and Programming

    Show the results of the following:

    (i)

    MOV A, #35H
ANL A, 0FH

    (ii)

    MOV A, #04H
ORL A, 03H

    (iii)

    MOV A, #54H
XRL A, A

    (iv)

    CLR C
MOV A, #26H
RRC A
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    Worked Solution

    Results of Given Instructions

    (i) MOV A,#35H; ANL A,0FH → A=35H & 0FH = 05H. Result A=05H, upper nibble masked.

    (ii) MOV A,#04H; ORL A,03H → 04H | 03H = 07H. A=07H (00000100 OR 00000011=00000111).

    (iii) MOV A,#54H; XRL A,A → Any value XOR itself = 00H. A=00H, zero flag implied but flags unchanged for logic? Actually XRL affects? In 8051 logic ops do not affect CY/OV, but parity updated.

    (iv) CLR C; MOV A,#26H; RRC A → A=26H=00100110B, C=0. RRC = rotate right through carry: new C= A0 (=0), A = (C old) concatenated >>1 = 0 0010011 = 13H. So A=13H, CY=0. If C started 0, result 13H. (If second rotation after? No). If assuming CLR C then RRC: A = 13H, C=0.

    Summary table:
    (i) 05H, (ii) 07H, (iii) 00H, (iv) 13H, CY=0.

  15. Q5a. Explain the different types of buses used in microprocessor.20227m

    Module 1: Fundamentals of Microprocessors

    Explain the different types of buses used in microprocessor.

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    Buses in Microprocessor

    • Address Bus: Unidirectional, carries address from CPU to memory/I/O. Size = addressing capacity (16-bit →64K). Example P2+P0 in 8051, A15-A0 in 8085.
    • Data Bus: Bidirectional, carries data CPU↔memory/peripherals. 8-bit in 8051/8085 AD7-0.
    • Control Bus: Carries control signals: \overline{RD}, \overline{WR}, ALE, IO/\overline{M}, \overline{PSEN}, \overline{EA}, READY, HOLD. Timing & control unit generates.

    Address selects device, control indicates read/write/I-O, data transfers. Multiplexed address/data reduces pins.

  16. Q5b. What is Subroutine? Explain the execution of Subroutine function.20227m

    Module 3: Instruction Set and Programming

    What is Subroutine? Explain the execution of Subroutine function.

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    Subroutine & Its Execution

    Definition: Subroutine (procedure/function) is reusable code block called from main via CALL, returns via RET/RETI.

    Execution in 8051:

    1. LCALL/ACALL addr pushes PC (return address) onto stack (SP++, low then high), loads subroutine address into PC, jumps.
    2. Subroutine executes; may use PUSH/POP to preserve registers.
    3. RET pops PC (high/low) from stack, resumes after CALL. RETI also clears interrupt priority for ISRs.

    Types: LCALL (16-bit), ACALL (11-bit page). Nesting limited by stack size. Benefits: modularity, code saving. Example:

    LCALL DELAY
;...
DELAY: MOV R7,#255
LOOP: DJNZ R7,LOOP
       RET
  17. Q6a. What do you mean by general purpose registers? Explain the various flags and status register in 8051.20227m

    Module 2: The 8051 Architecture

    What do you mean by general purpose registers? Explain the various flags and status register in 8051.

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    General Purpose Registers & Flags/PSW in 8051

    GPRs: Registers R0-R7 in 4 banks (00-07H,08-0FH,10-17H,18-1FH) selectable by RS1,RS0 (PSW.4-3). Plus Accumulator A, B, DPTR.

    PSW (D0H) flags: CY (PSW.7) carry/borrow, AC (PSW.6) auxiliary carry for BCD, FO (PSW.5) user flag, RS1/RS0 (bank select), OV (PSW.2) signed overflow, P (PSW.0) parity (1 if odd parity in A).

    SFRs: 21 SFRs as Q117. Categories: Ports, Timer (TMOD/TCON/THx/TLx), Serial (SCON/SBUF), Interrupt (IE/IP), Power (PCON), Control (PSW,SP,DPTR,ACC,B). Status register = PSW + SFRs.

  18. Q6b. List the various operations performed by the microprocessor.20227m

    Module 1: Fundamentals of Microprocessors

    List the various operations performed by the microprocessor.

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    Operations Performed by Microprocessor

    1. Data Transfer: Register↔memory/I/O (MOV, MOVX, PUSH/POP).
    2. Arithmetic: ADD, SUB, MUL, DIV, INC/DEC on binary/BCD.
    3. Logic: AND, OR, XOR, NOT, rotate, compare.
    4. Control/Branch: JMP, CALL, RET, conditional jumps.
    5. I/O Control: IN, OUT, port manipulation, serial.
    6. Timing & Control: Fetch-decode-execute sequencing, interrupt handling, bus control.
    7. Stack & Subroutine management.
  19. Q7a. Explain in detail about the addressing modes of 8051. Use example instructions for proper explanation.20227m

    Module 3: Instruction Set and Programming

    Explain in detail about the addressing modes of 8051. Use example instructions for proper explanation.

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    Addressing Modes of 8051 – Detail with Examples

    1. Immediate: MOV A,#0FFH
    2. Register: MOV A,R2, ADD A,R1
    3. Direct: MOV A,30H (internal RAM/SFR direct)
    4. Indirect: MOV A,@R0, MOV @R1,A, MOVX A,@DPTR
    5. Indexed: MOVC A,@A+DPTR, MOVC A,@A+PC
    6. Relative: SJMP REL, JZ REL, DJNZ R0,REL (-128..127)
    7. Absolute: AJMP addr11, ACALL
    8. Long: LJMP addr16, LCALL
    9. Bit: SETB P1.0, CLR ACC.2, MOV C,20H.3
    10. Implied: NOP, CPL A, RLC A

    Each distinguishes data source/destination encoding.

  20. Q7b. Explain the PSW flags and SFR's (Special function registers) of 8051 microcontroller and also write the type of SFR's.20227m

    Module 2: The 8051 Architecture

    Explain the PSW flags and SFR's (Special function registers) of 8051 microcontroller and also write the type of SFR's.

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    PSW Flags & SFR Types

    PSW flags (D0H, bit-addressable): CY (7) carry, AC (6) aux carry, F0(5) user, RS1(4) RS0(3) bank select, OV(2) overflow, - (1) reserved, P(0) parity. Flags updated by arithmetic/logic: ADD affects CY,AC,OV,P etc.

    SFR Types:

    • Port SFRs: P0,P1,P2,P3
    • Timer SFRs: TMOD,TCON,TH0,TL0,TH1,TL1
    • Serial SFRs: SCON,SBUF,PCON
    • Interrupt SFRs: IE,IP
    • Control SFRs: PSW,SP,ACC,B,DPL,DPH
    • Power/Misc: PCON

    21 core SFRs in 80-FFH, accessed by direct addressing only, 11 bit-addressable. Control whole MCU.

  21. Q8a. Define "OPCODE" and "OPERAND" with example. What do you understand by instruction set. Write the 3 categories of data transfer instructions.20227m

    Module 3: Instruction Set and Programming

    Define "OPCODE" and "OPERAND" with example. What do you understand by instruction set. Write the 3 categories of data transfer instructions.

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    OPCODE, OPERAND, Instruction Set & Data Transfer Categories

    • OPCODE (Operation Code): Specifies operation, e.g., MOV, ADD, encoded as binary. In MOV A,#55H, MOV opcode is 74H.
    • OPERAND: Data/address on which opcode acts, e.g., A, #55H, R0.

    Instruction Set: Entire collection of opcodes a CPU can execute (8051 has 111 instructions).

    3 Categories of Data Transfer:

    1. Immediate/Internal → Register: MOV A,#data, MOV R0,A
    2. Memory ↔ Register: MOVX A,@DPTR, MOVC, MOV A,@R0
    3. Stack/Exchange: PUSH, POP, XCH, XCHD
      (Also grouped as CPU↔RAM, CPU↔SFR/Port, CPU↔External.)
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  23. Q8b. Explain serial ports of 8051 microcontroller. Also discuss about registers used in serial communications.20227m

    Module 5: External Communication Interface

    Explain serial ports of 8051 microcontroller. Also discuss about registers used in serial communications.

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    Serial Ports of 8051 & Registers

    8051 has one full-duplex UART.

    Modes: Mode0 shift, Mode1 8-bit var baud, Mode2 9-bit fixed, Mode3 9-bit var.

    Registers:

    • SCON (98H): SM0,SM1 (mode), SM2 (mp), REN (enable), TB8,RB8, TI,RI.
    • SBUF (99H): Separate shift registers for TX/RX but same address; write starts TX, read gets RX.
    • PCON (87H.7 SMOD): Double baud bit.
    • TMOD/TH1/TL1/TCON: Timer1 sets baud in modes 1&3.
    • IE/IP: ES, PS for interrupt control.

    Baud: Mode0 Fosc/12, Mode2 Fosc/64 or /32, Modes1/3 via Timer1 overflow. Frame start/data/stop handles via flags TI/RI.

  24. Q9a. Write short notes on: Interrupts20227m

    Module 2: The 8051 Architecture

    Write short notes on: Interrupts

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    Short Notes: Interrupts (8051)

    • Sources 5 (INT0, T0, INT1, T1, Serial), vectors 0003-0023H, priority fixed via hardware polling but overridden by IP.
    • Enable via IE (EA global), request flags in TCON/SCON, trigger modes via ITx.
    • Response: finish instruction →push PC→vector →ISR→RETI pops.
    • Latency 3-8 cycles, nested allowed.
    • Applications: external events, timing, communication.
  25. Q9b. Write short notes on: I/O Ports20227m

    Module 2: The 8051 Architecture

    Write short notes on: I/O Ports

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    Worked Solution

    Short Notes: I/O Ports – see Q119/21

    4×8-bit ports P0-P3 quasi-bidirectional, P0 AD multiplexed, P2 high address, P3 alternates (RxD/TxD/INT/Timer/WR/RD), P1 pure I/O. Write 1 for input. Each port SFR latch+driver.

  26. Q9c. Write short notes on: Timers/Counters20227m

    Module 4: Memory and I/O Interfacing

    Write short notes on: Timers/Counters

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    Short Notes: Timers/Counters – see Q124

    2×16-bit T0/T1, TMOD/TLx/THx/TCON, modes 0-3, timer = Fosc/12, counter = external T0/T1 pulses, overflow TF→interrupt, used for delay, baud, event count.

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