2021 question paper
MICROPROCESSORS
21 questions
Q1a. Which output control signal is activated after every six oscillator periods while fetching the external program memory and almost remains high during internal program execution? (i) ALE (ii) \overline{PSEN} (iii) \overline{EA} (iv) All of the above20212m
Module 2: The 8051 Architecture
View this question on its own page →Which output control signal is activated after every six oscillator periods while fetching the external program memory and almost remains high during internal program execution?
(i) ALE
(ii)
(iii)
(iv) All of the aboveQ1b. What is the bit transmitting or receiving capability of mode 1 in serial communication? (i) 8 bits (ii) 10 bits (iii) 11 bits (iv) 12 bits20212m
Module 5: External Communication Interface
View this question on its own page →What is the bit transmitting or receiving capability of mode 1 in serial communication?
(i) 8 bits
(ii) 10 bits
(iii) 11 bits
(iv) 12 bitsQ1c. Which byte has the capability to interrupt the slave when SM2 bit is assigned to be '1' after the initialization process in the multiprocessor mode of communication? (i) Address byte (ii) Data byte (iii) Both (i) and (ii) (iv) None of the above20212m
Module 5: External Communication Interface
View this question on its own page →Which byte has the capability to interrupt the slave when SM2 bit is assigned to be '1' after the initialization process in the multiprocessor mode of communication?
(i) Address byte
(ii) Data byte
(iii) Both (i) and (ii)
(iv) None of the aboveQ1d. What can be the oscillator period for the multiplication operation of A and B in accordance to 16-bit product especially in B : A registers? (i) 12 (ii) 24 (iii) 36 (iv) 4820212m
Module 3: Instruction Set and Programming
View this question on its own page →What can be the oscillator period for the multiplication operation of A and B in accordance to 16-bit product especially in B : A registers?
(i) 12
(ii) 24
(iii) 36
(iv) 48Q1e. What is the possible range of transfer control for 8-bit relative address especially in 2's complement form with respect to the first byte of preceding instruction? (i) -115 to 132 bytes (ii) -130 to 132 bytes (iii) -128 to 127 bytes (iv) -115 to 127 bytes20212m
Module 3: Instruction Set and Programming
View this question on its own page →What is the possible range of transfer control for 8-bit relative address especially in 2's complement form with respect to the first byte of preceding instruction?
(i) -115 to 132 bytes
(ii) -130 to 132 bytes
(iii) -128 to 127 bytes
(iv) -115 to 127 bytesQ1f. Which operation is performed by stack pointer during its incremental phase? (i) Push (ii) Pop (iii) Return (iv) All of the above20212m
Module 2: The 8051 Architecture
View this question on its own page →Which operation is performed by stack pointer during its incremental phase?
(i) Push
(ii) Pop
(iii) Return
(iv) All of the aboveQ1g. Which version of MCS-51 requires the necessary connection of external clock source to XTAL2 in addition to the XTAL1 connectivity to ground level? (i) HMOS (ii) CHMOS (iii) CMOS (iv) All of the above20212m
Module 2: The 8051 Architecture
View this question on its own page →Which version of MCS-51 requires the necessary connection of external clock source to XTAL2 in addition to the XTAL1 connectivity to ground level?
(i) HMOS
(ii) CHMOS
(iii) CMOS
(iv) All of the aboveQ1h. What kind of triggering configuration of external interrupt intimate(s) the signal to stay low until the generation of subsequent interrupt? (i) Edge-triggering (ii) Level triggering (iii) Both (i) and (ii) (iv) None of the above20212m
Module 2: The 8051 Architecture
View this question on its own page →What kind of triggering configuration of external interrupt intimate(s) the signal to stay low until the generation of subsequent interrupt?
(i) Edge-triggering
(ii) Level triggering
(iii) Both (i) and (ii)
(iv) None of the aboveQ1i. Which lines are utilized during the enable state of hardware flow control in DTE and DCE devices of RS232? (i) CD and IR (ii) DSR and DTR (iii) RTS and CTS (iv) None of the above20212m
Module 5: External Communication Interface
View this question on its own page →Which lines are utilized during the enable state of hardware flow control in DTE and DCE devices of RS232?
(i) CD and IR
(ii) DSR and DTR
(iii) RTS and CTS
(iv) None of the aboveQ1j. Which protocol standard of serial communication specifies the bi-directional and half-duplex form of data transmission by allowing various numbers of drivers and receivers in bus configuration? (i) RS232 (ii) RS2485 (iii) RS422 (iv) RS42320212m
Module 5: External Communication Interface
View this question on its own page →Which protocol standard of serial communication specifies the bi-directional and half-duplex form of data transmission by allowing various numbers of drivers and receivers in bus configuration?
(i) RS232
(ii) RS2485
(iii) RS422
(iv) RS423Q2a. Write a program for 8051 to transmit "WELCOME TO INDIA" at the display connected to port 1 at 9600 baud for external crystal frequency of 11.0592 MHz.20217m
Module 5: External Communication Interface
View this question on its own page →Write a program for 8051 to transmit "WELCOME TO INDIA" at the display connected to port 1 at 9600 baud for external crystal frequency of 11.0592 MHz.
Q2b. Interface 4-digit seven-segment display with 8051 and write a program to display BCD number 1234 on it.20217m
Module 6: Applications
View this question on its own page →Interface 4-digit seven-segment display with 8051 and write a program to display BCD number 1234 on it.
Q3a. Write a program that converts odd parity bytes to even parity bytes (bit 7 is the parity bit).20217m
Module 3: Instruction Set and Programming
View this question on its own page →Write a program that converts odd parity bytes to even parity bytes (bit 7 is the parity bit).
Q3b. Assume you are determined to use mode 0 as a communication mode from one 8051 to another. Outline a system of hardware and software that would allow this.20217m
Module 5: External Communication Interface
View this question on its own page →Assume you are determined to use mode 0 as a communication mode from one 8051 to another. Outline a system of hardware and software that would allow this.
Q4a. How many 16-bit registers are available in 8051? Explain their functions.20217m
Module 2: The 8051 Architecture
View this question on its own page →How many 16-bit registers are available in 8051? Explain their functions.
Q4b. Name any four major differences between a microprocessor and a microcontroller.20214m
Module 1: Fundamentals of Microprocessors
View this question on its own page →Name any four major differences between a microprocessor and a microcontroller.
Q4c. Name 20 items that have a built-in microcontroller.20213m
Module 1: Fundamentals of Microprocessors
View this question on its own page →Name 20 items that have a built-in microcontroller.
Q6a. List the special function register associated with (i) Interrupts (ii) I/O ports (iii) Timers/Counters20217m
Module 2: The 8051 Architecture
View this question on its own page →List the special function register associated with
(i) Interrupts
(ii) I/O ports
(iii) Timers/CountersQ6b. Explain the concept of memory banks and further comment on the structure of the internal RAM of 8051.20217m
Module 2: The 8051 Architecture
View this question on its own page →Explain the concept of memory banks and further comment on the structure of the internal RAM of 8051.
Q7a. Enlist the salient features of the 8051 microcontroller.20217m
Module 1: Fundamentals of Microprocessors
View this question on its own page →Enlist the salient features of the 8051 microcontroller.
Q7b. What is the difference between over-flow and carry flag? Explain with an example.20217m
Module 2: The 8051 Architecture
View this question on its own page →What is the difference between over-flow and carry flag? Explain with an example.