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2021 question paper

MICROPROCESSORS

21 questions

  1. Q1a. Which output control signal is activated after every six oscillator periods while fetching the external program memory and almost remains high during internal program execution? (i) ALE (ii) \overline{PSEN} (iii) \overline{EA} (iv) All of the above20212m

    Module 2: The 8051 Architecture

    Which output control signal is activated after every six oscillator periods while fetching the external program memory and almost remains high during internal program execution?
    (i) ALE
    (ii) PSEN‾\overline{PSEN}
    (iii) EA‾\overline{EA}
    (iv) All of the above

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    Worked Solution

    Answer: (ii) \overline{PSEN}

    Explanation: \overline{PSEN} (Program Store Enable) is the 8051 control output that:

    • Pulses low once every 6 oscillator periods (once per machine cycle) when fetching code from external program memory.
    • Stays high (inactive, because it is active-low) almost continuously when execution is from internal program memory, going low only if an external access is needed.
    • ALE also pulses every 6 osc periods but is not specific to external code fetch and pulses even during internal execution (except when disabled). \overline{EA} is an input, not an output. Hence the description matches \overline{PSEN}.
  2. Q1b. What is the bit transmitting or receiving capability of mode 1 in serial communication? (i) 8 bits (ii) 10 bits (iii) 11 bits (iv) 12 bits20212m

    Module 5: External Communication Interface

    What is the bit transmitting or receiving capability of mode 1 in serial communication?
    (i) 8 bits
    (ii) 10 bits
    (iii) 11 bits
    (iv) 12 bits

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    Worked Solution

    Answer: (ii) 10 bits

    Explanation: 8051 Serial Mode 1 is the 8-bit UART mode (variable baud rate using Timer 1). Frame format = 1 start bit + 8 data bits + 1 stop bit = 10 bits per character. This contrasts with Mode 0 (8 bits shift register), Mode 2 (11 bits: 1 start + 8 data + 1 programmable 9th +1 stop), Mode 3 (11 bits similar to Mode 2 but variable baud). Thus Mode 1 transmits/receives 10-bit frames.

  3. Q1c. Which byte has the capability to interrupt the slave when SM2 bit is assigned to be '1' after the initialization process in the multiprocessor mode of communication? (i) Address byte (ii) Data byte (iii) Both (i) and (ii) (iv) None of the above20212m

    Module 5: External Communication Interface

    Which byte has the capability to interrupt the slave when SM2 bit is assigned to be '1' after the initialization process in the multiprocessor mode of communication?
    (i) Address byte
    (ii) Data byte
    (iii) Both (i) and (ii)
    (iv) None of the above

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    Worked Solution

    Answer: (i) Address byte

    Explanation: In 8051 multiprocessor mode (SM2=1), SCON bit SM2 enables filtering. When SM2=1 after initialization, the slave's RI is activated only if the received 9th bit (RB8) =1, which indicates an address byte (9th bit =1 marks address, 0 marks data). Data bytes (9th bit 0) do not interrupt slaves whose SM2=1 unless their address was previously matched (then SM2 is cleared by software). Thus only address byte interrupts all slaves when SM2=1.

  4. Q1d. What can be the oscillator period for the multiplication operation of A and B in accordance to 16-bit product especially in B : A registers? (i) 12 (ii) 24 (iii) 36 (iv) 4820212m

    Module 3: Instruction Set and Programming

    What can be the oscillator period for the multiplication operation of A and B in accordance to 16-bit product especially in B : A registers?
    (i) 12
    (ii) 24
    (iii) 36
    (iv) 48

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    Worked Solution

    Answer: (iv) 48

    Explanation: 8051 MUL AB multiplies unsigned 8-bit A × B → 16-bit product in B:A (B high, A low). Execution time is 4 machine cycles. At 12 oscillator periods per machine cycle (traditional 8051), 4×12 = 48 oscillator periods. Hence option (iv) 48. (Some CMOS variants 6T mode differ, but exam expects 48.)**

  5. Q1e. What is the possible range of transfer control for 8-bit relative address especially in 2's complement form with respect to the first byte of preceding instruction? (i) -115 to 132 bytes (ii) -130 to 132 bytes (iii) -128 to 127 bytes (iv) -115 to 127 bytes20212m

    Module 3: Instruction Set and Programming

    What is the possible range of transfer control for 8-bit relative address especially in 2's complement form with respect to the first byte of preceding instruction?
    (i) -115 to 132 bytes
    (ii) -130 to 132 bytes
    (iii) -128 to 127 bytes
    (iv) -115 to 127 bytes

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    Worked Solution

    Answer: (iii) -128 to 127 bytes

    Explanation: Relative addressing in 8051 (SJMP, conditional jumps JC/JNC, JZ/JNZ, DJNZ, CJNE) uses an 8-bit signed offset added to PC after fetching the jump instruction. 8-bit 2's complement range is -128 to +127 bytes relative to the first byte of the next instruction (PC after fetch). Some textbooks quote -128 to +127 relative to current PC. Hence the range is -128 to +127.

  6. Q1f. Which operation is performed by stack pointer during its incremental phase? (i) Push (ii) Pop (iii) Return (iv) All of the above20212m

    Module 2: The 8051 Architecture

    Which operation is performed by stack pointer during its incremental phase?
    (i) Push
    (ii) Pop
    (iii) Return
    (iv) All of the above

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    Worked Solution

    Answer: (i) Push

    Explanation: In 8051, stack grows upward. PUSH increments SP first, then stores byte: SP←SP+1; [SP]←src. POP decrements after read: dst←[SP]; SP←SP-1. So incremental phase corresponds to PUSH. RET/POP decrement SP.

  7. Q1g. Which version of MCS-51 requires the necessary connection of external clock source to XTAL2 in addition to the XTAL1 connectivity to ground level? (i) HMOS (ii) CHMOS (iii) CMOS (iv) All of the above20212m

    Module 2: The 8051 Architecture

    Which version of MCS-51 requires the necessary connection of external clock source to XTAL2 in addition to the XTAL1 connectivity to ground level?
    (i) HMOS
    (ii) CHMOS
    (iii) CMOS
    (iv) All of the above

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    Worked Solution

    Answer: (i) HMOS

    Explanation: HMOS version of MCS-51 (e.g., 8051 original) requires an external clock source to be connected to XTAL2 with XTAL1 grounded when driven externally. CHMOS/CMOS versions (80C51) use XTAL1 as clock input and leave XTAL2 floating. Hence HMOS is the version described.

  8. Q1h. What kind of triggering configuration of external interrupt intimate(s) the signal to stay low until the generation of subsequent interrupt? (i) Edge-triggering (ii) Level triggering (iii) Both (i) and (ii) (iv) None of the above20212m

    Module 2: The 8051 Architecture

    What kind of triggering configuration of external interrupt intimate(s) the signal to stay low until the generation of subsequent interrupt?
    (i) Edge-triggering
    (ii) Level triggering
    (iii) Both (i) and (ii)
    (iv) None of the above

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    Worked Solution

    Answer: (ii) Level triggering

    Explanation: External interrupts INT0/INT1 can be edge-triggered (IT0/IT1=1, falling edge) or level-triggered (IT0/IT1=0, low level). Level-triggered requires the signal to stay low until the interrupt is serviced and the external source releases it; otherwise repeated interrupts or missed flag clearing occur. Edge-triggered needs only a falling edge.

  9. Q1i. Which lines are utilized during the enable state of hardware flow control in DTE and DCE devices of RS232? (i) CD and IR (ii) DSR and DTR (iii) RTS and CTS (iv) None of the above20212m

    Module 5: External Communication Interface

    Which lines are utilized during the enable state of hardware flow control in DTE and DCE devices of RS232?
    (i) CD and IR
    (ii) DSR and DTR
    (iii) RTS and CTS
    (iv) None of the above

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    Worked Solution

    Answer: (iii) RTS and CTS

    Explanation: In RS232 hardware flow control, RTS (Request To Send) and CTS (Clear To Send) are cross-coupled: DTE's RTS → DCE's CTS and vice-versa. When both enabled, data is transmitted only when RTS/CTS handshake is asserted (active low). DSR/DTR are modem readiness, CD is carrier detect.

  10. Q1j. Which protocol standard of serial communication specifies the bi-directional and half-duplex form of data transmission by allowing various numbers of drivers and receivers in bus configuration? (i) RS232 (ii) RS2485 (iii) RS422 (iv) RS42320212m

    Module 5: External Communication Interface

    Which protocol standard of serial communication specifies the bi-directional and half-duplex form of data transmission by allowing various numbers of drivers and receivers in bus configuration?
    (i) RS232
    (ii) RS2485
    (iii) RS422
    (iv) RS423

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    Worked Solution

    Answer: (ii) RS485 (option typed as RS2485)

    Explanation: RS485 is the bi-directional half-duplex differential bus standard allowing up to 32 drivers/32 receivers on same bus, ideal for multi-drop networks. RS232 is single-ended point-to-point, RS422 is differential but unidirectional multi-drop (one driver, multiple receivers), RS423 similar. The typo RS2485 means RS485.

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  12. Q2a. Write a program for 8051 to transmit "WELCOME TO INDIA" at the display connected to port 1 at 9600 baud for external crystal frequency of 11.0592 MHz.20217m

    Module 5: External Communication Interface

    Write a program for 8051 to transmit "WELCOME TO INDIA" at the display connected to port 1 at 9600 baud for external crystal frequency of 11.0592 MHz.

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    Worked Solution

    Program to transmit "WELCOME TO INDIA" at 9600 baud, 11.0592 MHz, display on port 1 (serial transmission example)

    Baud 9600 with 11.0592 MHz → Timer 1 mode 2, TH1 = 0FDH, SMOD=0 → 9600. Mode 1 (8-bit UART). Assume display is serial via TXD or port 1 is shown after reception - here we transmit via SBUF repeatedly.

    ; 8051 Assembly - Transmit string via serial Mode 1 at 9600 baud
ORG 0000H
LJMP MAIN
ORG 0030H
MAIN: MOV TMOD,#20H   ; Timer1 mode2 auto-reload
      MOV TH1,#0FDH   ; 9600 baud @11.0592MHz
      MOV TL1,#0FDH
      MOV SCON,#50H   ; mode1, 8-bit, REN=1
      MOV PCON,#00H   ; SMOD=0
      SETB TR1        ; start timer1
      MOV DPTR,#MSG
NEXT: CLR A
      MOVC A,@A+DPTR  ; fetch char
      JZ STOP         ; 0 terminator end
      ACALL TRANSMIT
      MOV P1,A        ; also display on port1 as per question
      INC DPTR
      SJMP NEXT
STOP: SJMP STOP
TRANSMIT: MOV SBUF,A
WAIT:   JNB TI,WAIT
        CLR TI
        RET
MSG: DB "WELCOME TO INDIA",0
END

    C (Keil) alternative:

    #include <reg51.h>
void uart_init(){ TMOD=0x20; TH1=0xFD; SCON=0x50; PCON=0x00; TR1=1; }
void tx(char c){ SBUF=c; while(!TI); TI=0; P1=c; }
void main(){ uart_init(); char *s="WELCOME TO INDIA"; while(*s) tx(*s++); while(1);}

    Calculation: Baud = (2^SMOD/32)(Fosc/12/(256-TH1)). With TH1=FDH (253), Fosc=11.0592M → (1/32)(11059200/12/3)=9600. Error 0%.

  13. Q2b. Interface 4-digit seven-segment display with 8051 and write a program to display BCD number 1234 on it.20217m

    Module 6: Applications

    Interface 4-digit seven-segment display with 8051 and write a program to display BCD number 1234 on it.

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    Worked Solution

    4-Digit Seven-Segment Display Interface with 8051 + Program to Display 1234

    Hardware: Common anode/cathode displays via BCD to 7-seg decoder (7447) or direct port driving via current limiting resistors. Use multiplexing: Segments (a-g,dp) to P0 (8 bits), Digit common (COM1-4) via NPN/ULN2003 to P2.0-P2.3. Or use 8255.

    Connections: P0.0-P0.7 → a,b,c,d,e,f,g,+dp (or via 74LS244), P2.0→DIG1, P2.1→DIG2, etc., active low/high depending on type. Use multiplexing: enable one digit at a time ~5 ms persistence.

    Program (Assembly) to display 1234:

    ORG 0000H
MOV P0,#00H
MOV P2,#00H
MAIN: MOV DPTR,#SEG_TABLE
      MOV R0,#01H ; digit 1 = "1"
      MOV R1,#02H ; digit 2 = "2" etc for demo constant 1234
; Multiplex loop
LOOP: MOV A,#01H ; enable DIG1
      MOV P2,A
      MOV A,#06H ; code for "1" (common cathode 06H) from table
      MOV P0,A
      ACALL DELAY_5MS
      MOV A,#02H ; DIG2
      MOV P2,A
      MOV A,#5BH ; "2"
      MOV P0,A
      ACALL DELAY_5MS
      MOV A,#04H ; DIG3 "3"
      MOV P2,A
      MOV A,#4FH
      MOV P0,A
      ACALL DELAY_5MS
      MOV A,#08H ; DIG4 "4"
      MOV P2,A
      MOV A,#66H
      MOV P0,A
      ACALL DELAY_5MS
      SJMP LOOP
SEG_TABLE: DB 3FH,06H,5BH,4FH,66H,6DH,7DH,07H,7FH,6FH ; 0-9 CC
DELAY_5MS: MOV TH0,#0EEH ; as before
           MOV TL0,#00H
           SETB TR0
W:         JNB TF0,W
           CLR TR0
           CLR TF0
           RET
END

    Generic BCD display routine: Fetch BCD nibbles from memory, look up segment codes, multiplex digits sequentially. Time-division multiplexing with persistence gives steady 1234 view.

  14. Q3a. Write a program that converts odd parity bytes to even parity bytes (bit 7 is the parity bit).20217m

    Module 3: Instruction Set and Programming

    Write a program that converts odd parity bytes to even parity bytes (bit 7 is the parity bit).

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    Worked Solution

    Program: Convert odd-parity bytes to even-parity (bit7 is parity bit)

    Odd parity means total 1s (including bit7) odd; even parity means total 1s even. Convert by toggling bit7 if needed.

    ORG 0000H
MOV R0,#30H ; source array start
MOV R1,#40H ; destination or same buffer
MOV R2,#10H ; count = 16 bytes example
LOOP: MOV A,@R0
      MOV C,P   ; P = parity flag (PSW.0) =1 if odd parity in A
      ; For odd parity bytes, P=1, for even P=0
      ; We want to ensure even parity in result (including bit7)
      ; If current parity is odd (P=1) with current bit7, then need to toggle bit7
      ; Actually if accumulator currently has odd parity (P=1), then total 1s odd -> to make even, flip bit7
      JNB P,NEXT ; if already even, keep bit7
      CPL ACC.7  ; invert parity bit
NEXT: MOV @R1,A
      INC R0
      INC R1
      DJNZ R2,LOOP
      SJMP $
END

    Logic: P flag reflects parity of A. For each byte, if P=1 (odd), complement bit7 to make even parity; if P=0 leave. This swaps odd→even. Alternative sequence: ANL A,#7FH to clear bit7, then set bit7 to make even; but above correctly toggles.

  15. Q3b. Assume you are determined to use mode 0 as a communication mode from one 8051 to another. Outline a system of hardware and software that would allow this.20217m

    Module 5: External Communication Interface

    Assume you are determined to use mode 0 as a communication mode from one 8051 to another. Outline a system of hardware and software that would allow this.

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    Worked Solution

    System to Use Mode 0 Between Two 8051s (Synchronous Shift Register)

    Mode 0 is 8-bit synchronous shift register via RxD (data) and TxD (shift clock). To interconnect two 8051s:

    Hardware: Cross-connect: Master’s RxD (P3.0) ↔ Slave’s RxD? Actually Mode 0: TX and RX share same pin RxD for data, TxD outputs clock. Connect:

    • Master TxD (clock) → Slave TxD (clock) (both open-drain, need common clock source – mode 0 is half-duplex, so only one side generates clock).
    • Master RxD → Slave RxD (data line) bidirectional via buffer.
      Better: Use extra handshaking lines (P3.2/3.3) for direction control because clock is only generated during transmission by the sender.

    Software: Master config: SCON=0x00 (mode0), sender loads SBUF, hardware clocks 8 bits; slave also SCON=0x00 with REN=1 to receive. Poll TI/RI or interrupt. Add protocol: Master asserts handshake line → slave prepares, then Master writes SBUF, waits TI, Slave reads SBUF after RI, acknowledge. Bit rate = Fosc/12. Direction reversal requires swapping master/slave role.

    Limitations: Not full-duplex; need external direction control and synchronization; suitable for short distance board-to-board; for robust, prefer modes 1-3.

  16. Q4a. How many 16-bit registers are available in 8051? Explain their functions.20217m

    Module 2: The 8051 Architecture

    How many 16-bit registers are available in 8051? Explain their functions.

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    Worked Solution

    16-bit Registers in 8051

    8051 has two main 16-bit registers: DPTR (Data Pointer) and PC (Program Counter). SP is 8-bit but points to 8-bit addresses. Some count also Timer0/1 (THx:TLx) as 16-bit counters.

    1. DPTR (DPL 82H + DPH 83H): 16-bit pointer for external data/code access (MOVX A,@DPTR, MOVC A,@A+DPTR). Can be incremented (INC DPTR) and used as two 8-bit registers.
    2. PC (16-bit): Holds next fetch address, invisible to direct move but affected by LJMP, etc.
    3. Timer0 & Timer1: Each 16-bit (TH0:TL0, TH1:TL1) for timing/counting, baud generation.
      If counting broadly, 4×16-bit including timers.

    Functions: Addressing 64K external memory, sequencing code, timing, stack is 8-bit but extended via DPTR manipulation.

  17. Q4b. Name any four major differences between a microprocessor and a microcontroller.20214m

    Module 1: Fundamentals of Microprocessors

    Name any four major differences between a microprocessor and a microcontroller.

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    Worked Solution

    Microprocessor vs Microcontroller – 4 Differences

    Aspect Microprocessor Microcontroller
    1. Integration CPU only, needs external memory/I/O CPU+RAM+ROM+I/O+timers on single chip
    2. Cost/Size Higher system cost, larger PCB Low cost, compact
    3. Applications General-purpose computing (PC) Dedicated control (appliances, automotive)
    4. Power & Performance High speed, high power Low-mid speed, low power
    Extra: MP uses Von Neumann external buses, MC Harvard on-chip. MP needs more support ICs, MC single-chip.
  18. Q4c. Name 20 items that have a built-in microcontroller.20213m

    Module 1: Fundamentals of Microprocessors

    Name 20 items that have a built-in microcontroller.

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    Worked Solution

    20 Items with Built-in Microcontroller

    1. Washing machine 2. Microwave oven 3. TV remote / TV 4. Air conditioner 5. Automobile ECU (ABS, engine) 6. Mobile phone 7. Printer 8. Keyboard/mouse 9. MP3 player 10. Digital camera 11. Elevator controller 12. Pacemaker 13. Smart watch 14. Traffic light controller 15. ATM machine 16. Digital thermometer 17. Toys (RC) 18. Solar inverter 19. Drone 20. Smart meter / IoT sensor node.
  19. Q6a. List the special function register associated with (i) Interrupts (ii) I/O ports (iii) Timers/Counters20217m

    Module 2: The 8051 Architecture

    List the special function register associated with
    (i) Interrupts
    (ii) I/O ports
    (iii) Timers/Counters

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    Worked Solution

    SFRs for Interrupts, I/O, Timers

    • Interrupts: IE A8H (enable: EA,ES,ET1,EX1,ET0,EX0), IP B8H (priority: PS,PT1,PX1,PT0,PX0), TCON 88H (flags IE1/IE0, IT1/IT0, TF1/TR1,TF0/TR0), SCON 98H (TI/RI for serial interrupt).
    • I/O Ports: P0 80H, P1 90H, P2 A0H, P3 B0H – latches + alternate control via SCON/TCON.
    • Timers/Counters: TMOD 89H (mode/GATE/C/T/M1M0 for both), TCON 88H (TF/TR/IE/IT), TH0/TL0 8CH/8AH, TH1/TL1 8DH/8BH, PCON 87H (T2 extra in 8052: T2CON etc.).

    Set via MOV IE,#... ; MOV TMOD,#... ; MOV P1,#... etc.

  20. Q6b. Explain the concept of memory banks and further comment on the structure of the internal RAM of 8051.20217m

    Module 2: The 8051 Architecture

    Explain the concept of memory banks and further comment on the structure of the internal RAM of 8051.

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    Worked Solution

    Memory Banks & Internal RAM Structure (8051)

    Register Banks: 4 banks × 8 registers R0-R7 mapped 00-1FH: Bank0 00-07H, Bank1 08-0FH, Bank2 10-17H, Bank3 18-1FH. Selected by RS1 RS0 (PSW.4-3). Fast context switch for interrupts without PUSH.

    Internal RAM 128B (00-7FH) or 256B (8052 00-FFH):

    • 00-1FH banks (32B)
    • 20-2FH bit-addressable 16B (128 bits, bit addr 00-7FH) for flags/semaphores.
    • 30-7FH general scratch.
    • 80-FFH SFRs (separate space, direct address only). In 8052, 80-FFH upper RAM accessible via indirect (@R0) vs SFR via direct.

    Stack typically relocated to 30H+ to avoid bank collision; SP=07H default shares with bank1.

  21. Q7a. Enlist the salient features of the 8051 microcontroller.20217m

    Module 1: Fundamentals of Microprocessors

    Enlist the salient features of the 8051 microcontroller.

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    Worked Solution

    Salient Features of 8051

    8-bit CPU, 4KB ROM, 128B RAM, 32 I/O lines (4 ports), 2×16-bit timers, 5 interrupts (2 external), full-duplex UART, 64K program+64K data, boolean processor with bit operations, 111 instructions (49 single-byte), 1µs cycle @12MHz, single supply +5V, 40-pin DIP, Harvard, 4 register banks, bit-addressable RAM/SFRs, power save (Idle/Power-down), commercial/industrial temp.

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  23. Q7b. What is the difference between over-flow and carry flag? Explain with an example.20217m

    Module 2: The 8051 Architecture

    What is the difference between over-flow and carry flag? Explain with an example.

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    Worked Solution

    Carry (CY) vs Overflow (OV) – Difference with Example

    • CY (PSW.7): Unsigned overflow – carry out of bit7. 1 if result exceeds 255 (addition) or borrow in subtraction. For unsigned numbers.
    • OV (PSW.2): Signed overflow – carry into sign bit XOR carry out. 1 if signed result exceeds -128..127. For signed 2's complement.

    Example:

    1. MOV A,#0FFH; ADD A,#01H → A=00H, CY=1 (unsigned overflow 255+1), AC=1, OV=0 (signed -1+1=0 no overflow). CY indicates unsigned wrap.
    2. MOV A,#7FH; ADD A,#01H → A=80H, CY=0 (no unsigned overflow), OV=1 (signed 127+1 = -128 overflow). This shows signed overflow without carry.

    Check: OV = CY6 XOR CY7.

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