2020 question paper

MICROPROCESSORS

24 questions

1. Q1a. Which among the below mentioned functions does not belong to the category of alternate functions usually performed by Port 3 (Pins 10-17)? (i) External interrupts (ii) Internal interrupts (iii) Serial ports (iv) Read/Write control signals20202m

   Module 2: The 8051 Architecture

   Which among the below mentioned functions does not belong to the category of alternate functions usually performed by Port 3 (Pins 10-17)?
   (i) External interrupts
   (ii) Internal interrupts
   (iii) Serial ports
   (iv) Read/Write control signals

   View this question on its own page →

   CopySearch GoogleAsk AI

   Worked Solution

   Answer: (ii) Internal interrupts

   Explanation: Port 3 (P3.0–P3.7, pins 10–17) in 8051 has alternate functions:

   • P3.0 = RxD (serial input), P3.1 = TxD (serial output) → serial ports
   • P3.2 = INT0, P3.3 = INT1\ → external interrupts
   • P3.4 = T0, P3.5 = T1 (timer inputs)
   • P3.6 = WR, P3.7 = RD\ → external memory read/write strobes

   There is no alternate function for "internal interrupts" on Port 3. All other options are valid Port-3 alternate functions. Hence (ii) does not belong.

2. Q1b. Why are the resonators not preferred for an oscillator circuit of 8051? (i) Because they do not avail for 12 MHz higher order frequencies (ii) Because they are unstable as compared to quartz crystals (iii) Because cost reduction due to its utility is almost negligible in comparison to total cost of microcontroller board (iv) All of the above20202m

   Module 2: The 8051 Architecture

   Why are the resonators not preferred for an oscillator circuit of 8051?
   (i) Because they do not avail for 12 MHz higher order frequencies
   (ii) Because they are unstable as compared to quartz crystals
   (iii) Because cost reduction due to its utility is almost negligible in comparison to total cost of microcontroller board
   (iv) All of the above

   View this question on its own page →

   CopySearch GoogleAsk AI

   Worked Solution

   Answer: (iv) All of the above

   Explanation: Crystal oscillators (quartz) are preferred over ceramic resonators for 8051 because:

   1. Ceramic resonators are available with lower frequency accuracy and do not reliably offer 12 MHz and higher frequencies with required stability.
   2. Resonators are less stable over temperature and aging compared to quartz crystals, causing baud-rate and timing errors.
   3. The cost saving of a resonator vs crystal is negligible compared to overall MCU board cost, so there is no compelling cost advantage.
      Hence all statements are true, resonators are not preferred.
3. Q1c. Which serial modes possess the potential to support the multi-processor type of communication? (i) Modes 0 & 1 (ii) Modes 1 & 2 (iii) Modes 2 & 3 (iv) All of the above20202m

   Module 5: External Communication Interface

   Which serial modes possess the potential to support the multi-processor type of communication?
   (i) Modes 0 & 1
   (ii) Modes 1 & 2
   (iii) Modes 2 & 3
   (iv) All of the above

   View this question on its own page →

   CopySearch GoogleAsk AI

   Worked Solution

   Answer: (iii) Modes 2 & 3

   Explanation: 8051 serial modes 2 and 3 are 9-bit UART modes (1 start + 8 data + 1 programmable 9th bit + 1 stop = 11 bits) that support ** multiprocessor communication** using the 9th bit and SM2 feature to distinguish address vs data bytes. Mode 0 is shift register (synchronous) and Mode 1 is 8-bit UART (10 bits) - both lack the 9th bit mechanism for multiprocessor addressing. Hence only Modes 2 & 3 support multiprocessor communication.

4. Q1d. Which flag allows to carry out the signed as well as unsigned addition and subtraction operations? (i) CY (ii) OV (iii) AC (iv) FO20202m

   Module 2: The 8051 Architecture

   Which flag allows to carry out the signed as well as unsigned addition and subtraction operations?
   (i) CY
   (ii) OV
   (iii) AC
   (iv) FO

   View this question on its own page →

   CopySearch GoogleAsk AI

   Worked Solution

   Answer: (ii) OV

   Explanation: OV (Overflow) flag in PSW (PSW.2) indicates signed overflow (carry into sign bit XOR carry out). To correctly detect signed addition/subtraction results, OV is examined along with CY for unsigned. CY alone handles unsigned carry/borrow. AC is auxiliary carry for BCD, FO is user flag (PSW.5). So OV allows both signed and unsigned operations to be distinguished (e.g., ADD vs ADDC with overflow check).**

5. Q1e. Which among the single operand instructions complements the accumulator without affecting any of the flags? (i) CLR (ii) SETB (iii) CPL (iv) All of the above20202m

   Module 3: Instruction Set and Programming

   Which among the single operand instructions complements the accumulator without affecting any of the flags?
   (i) CLR
   (ii) SETB
   (iii) CPL
   (iv) All of the above

   View this question on its own page →

   CopySearch GoogleAsk AI

   Worked Solution

   Answer: (iii) CPL

   Explanation: CPL A (Complement Accumulator) does A = ~A (ones complement) and affects no flags. CLR A clears A to 0 and also no flags but not complement. SETB sets a bit flag. Complement operations in 8051 (CPL A, CPL C, CPL bit) are defined to leave PSW flags unchanged (except CPL C complements Carry). For single-operand complement of accumulator without flag change, CPL A is correct.

6. Q1f. Which register usually stores the output generated by ALU in several arithmetic and logical operations? (i) Accumulator (ii) Special function register (iii) Timer register (iv) Stack pointer20202m

   Module 2: The 8051 Architecture

   Which register usually stores the output generated by ALU in several arithmetic and logical operations?
   (i) Accumulator
   (ii) Special function register
   (iii) Timer register
   (iv) Stack pointer

   View this question on its own page →

   CopySearch GoogleAsk AI

   Worked Solution

   Answer: (i) Accumulator

   Explanation: Accumulator (ACC, A register, address E0H) is the primary working register for ALU in 8051 and 8085. Most arithmetic-logic operations take one operand from A and store result back into A. SFR, Timer, SP do not hold ALU results.

7. Q1g. What is the required baud rate for an efficient operation of serial port devices in 8051 microcontroller? (i) 1200 (ii) 2400 (iii) 4800 (iv) 960020202m

   Module 5: External Communication Interface

   What is the required baud rate for an efficient operation of serial port devices in 8051 microcontroller?
   (i) 1200
   (ii) 2400
   (iii) 4800
   (iv) 9600

   View this question on its own page →

   CopySearch GoogleAsk AI

   Worked Solution

   Answer: (iv) 9600 (standard; others also usable but exam expects 9600)

   Explanation: For 8051 serial communication with 11.0592 MHz crystal, the common efficient baud rates generated by Timer 1 are 1200/2400/4800/9600/19200. 9600 baud (with TH1 = 0FDH, SMOD=0, Timer1 mode 2) is the most widely used reliable default for serial port devices (PC, GSM, Bluetooth modules). Higher rates like 9600 balance speed and error (<0% error at 11.0592 MHz). Hence (iv) is considered required/efficient.

8. Q1h. How does the microcontroller communicate with the external peripherals/memory? (i) Via I/O ports (ii) Via register arrays (iii) Via memory (iv) All of the above20202m

   Module 4: Memory and I/O Interfacing

   How does the microcontroller communicate with the external peripherals/memory?
   (i) Via I/O ports
   (ii) Via register arrays
   (iii) Via memory
   (iv) All of the above

   View this question on its own page →

   CopySearch GoogleAsk AI

   Worked Solution

   Answer: (i) Via I/O ports

   Explanation: 8051 communicates with external peripherals/memory via its 32 I/O lines (P0-P3). Port 0 & Port 2 provide multiplexed address/data buses, Port 3 provides control signals (RD, WR), while data transfer occurs through port pins. Register arrays are internal.

9. Q1i. How are the address and data buses removed in external memory type of microcontrollers? (i) Through demultiplexing by external latch & ALE signal (ii) Through demultiplexing by external latch & DLE signal (iii) Through multiplexing by external latch & DLE signal (iv) Through multiplexing by external latch & ALE signal20202m

   Module 4: Memory and I/O Interfacing

   How are the address and data buses removed in external memory type of microcontrollers?
   (i) Through demultiplexing by external latch & ALE signal
   (ii) Through demultiplexing by external latch & DLE signal
   (iii) Through multiplexing by external latch & DLE signal
   (iv) Through multiplexing by external latch & ALE signal

   View this question on its own page →

   CopySearch GoogleAsk AI

   Worked Solution

   Answer: (i) Through demultiplexing by external latch & ALE signal

   Explanation: Port 0 multiplexes A0-A7/D0-D7. At start of external memory cycle, ALE high latches A0-A7 into 74LS373. When ALE falls, Port 0 becomes data bus. Thus address and data are demultiplexed using external latch driven by ALE. Not DLE, not multiplexing.

10. Q1j. What are the essential tight constraints related to the design metrics of an embedded system? (i) Ability to fit on a single chip (ii) Low power consumption (iii) Fast data processing for real-time operations (iv) All of the above20202m

    Module 1: Fundamentals of Microprocessors

    What are the essential tight constraints related to the design metrics of an embedded system?
    (i) Ability to fit on a single chip
    (ii) Low power consumption
    (iii) Fast data processing for real-time operations
    (iv) All of the above

    View this question on its own page →

    CopySearch GoogleAsk AI

    Worked Solution

    Answer: (iv) All of the above

    Explanation: Embedded system design metrics are tightly constrained: single-chip integration (size/cost), low power (battery operation), and real-time fast processing. Additional constraints include reliability, cost, NRE, flexibility. Hence all listed are essential constraints.

11. Budget App•POCKETLY

    Pocketly on Android

    Log daily food, travel, and hostel expenses instantly. Set monthly spending limits and see where your money goes without complex spreadsheets.

    Install Pocketly
12. Q2a. Interface 16 kB of ROM and 8 kB of RAM with 8051 microcontroller. Write their address range.20207m

    Module 4: Memory and I/O Interfacing

    Interface 16 kB of ROM and 8 kB of RAM with 8051 microcontroller. Write their address range.

    View this question on its own page →

    CopySearch GoogleAsk AI

    Worked Solution

    Interface 16 KB ROM + 8 KB RAM with 8051

    8051 has separate program (\overline{PSEN}) and data (\overline{RD}/\overline{WR}) spaces, each 64KB. Typically ROM as program memory and RAM as data memory.

    Option 1: Both as program/data expansion using external memory (most exam expects unified external):

    • 16 KB ROM (e.g., 27128): Needs 14 address lines A0-A13. Connected to P0 (AD0-AD7 latched) + P2.0-P2.5 (A8-A13). \overline{PSEN} or \overline{RD} as OE. Address range example if starting at 0000H:
      0000H – 3FFFH (16384 bytes) for 16KB.
      Next free from 4000H.
    • 8 KB RAM (e.g., 6264): Needs 13 lines A0-A12. If contiguous after ROM:
      4000H – 5FFFH (8192 bytes) for 8KB.
      Using \overline{RD} and \overline{WR} for OE/WE. Chip select via decoder (74LS138) or simple linear P2.6/P2.7.

    Full decoding example via 74LS138 (A15-A13):

    • ROM CS = Y0 → 0000H-1FFFH for 8K? But for 16K, use A14=0 block. Simpler: A15=0 for lower 32K. Many textbooks show:
      ROM 16K: 0000H–3FFFH ( \overline{PSEN} ), RAM 8K: 8000H–9FFFH (using P2.7=1) to avoid overlap with different spaces. Because program and data spaces are separate, same address can be reused; the range is logical. If both as data memory (MOVX), same ranges but using \overline{RD}/\overline{WR}.

    Hardware: Port 0 via 74LS373 latched by ALE provides A0-A7, Port 2 provides A8-A15, \overline{EA}=1 for internal + external, or 0 for only external. Connect ROM OE to \overline{PSEN} (program) or RAM OE to \overline{RD}.

    Address map summary (one common textbook arrangement):

    • 16KB ROM: 0000H to 3FFFH
    • 8KB RAM: 4000H to 5FFFH (or 0000H-1FFFH in data space if separate buses - then no conflict)
      Calculation: 16KB=2^14 → last = start+3FFFH; 8KB=2^13 → last = start+1FFFH.
      If you place RAM at 0000H data space, its range is 0000H-1FFFH distinct from program ROM.

    Diagram: P0→373→A0-A7→ROM/RAM, P2→A8-A15, ALE→373 LE, \overline{PSEN}→ROM OE, \overline{RD}/\overline{WR}→RAM OE/WE, CS decoded from high address lines.

    Any contiguous non-overlapping 14-bit/13-bit block is acceptable if decoding explained.

13. Q2b. What value should be loaded into timer register so as to have a time delay of 5 ms? Write a program to create a pulse width of 5 ms on pin P2.3. Assume crystal frequency to be 11.0592 MHz.20207m

    Module 6: Applications

    What value should be loaded into timer register so as to have a time delay of 5 ms? Write a program to create a pulse width of 5 ms on pin P2.3. Assume crystal frequency to be 11.0592 MHz.

    View this question on its own page →

    CopySearch GoogleAsk AI

    Worked Solution

    5 ms Delay Calculation & Program for P2.3 Pulse (11.0592 MHz)

    Machine cycle: Fosc/12 = 11059200/12 = 921600 Hz → Tcy = 1.085 µs. Timer increments every 1.085 µs.
    Counts needed for 5 ms = 5ms /1.085us = 4608 decimal = 1200H.
    For 16-bit timer mode 1: TH:TL = 10000H - 1200H = EE00H. So TH=0EEH, TL=00H. For mode 1 with auto-reload? Use TL load accordingly. Alternative using 50 counts errors small.
    If using Timer 0 mode 1:
    TH0 = 0EEH, TL0 = 00H yields 5 ms.
    For 5 ms high pulse on P2.3:

    ORG 0000H
    MAIN: MOV TMOD,#01H ; T0 mode1 16-bit
    LOOP: SETB P2.3
          MOV TH0,#0EEH
          MOV TL0,#00H
          SETB TR0
    WAIT: JNB TF0,WAIT
          CLR TR0
          CLR TF0
          CLR P2.3     ; after 5ms low (or keep high pulse 5ms)
          MOV TH0,#0EEH
          MOV TL0,#00H
          SETB TR0
    WAIT2:JNB TF0,WAIT2
          CLR TR0
          CLR TF0
          SJMP LOOP
    END
    

    Alternative C: TH0=0xEE; TL0=0x00; loop. If using 12 MHz crystal, Tcy=1us, counts=5000=1388H, TH=0ECH, TL=78H.
    Note: For exact 5ms pulse, set P2.3 high, delay, clear, delay.
    If only delay value asked: 4608 counts → EE00H reload.

14. Q3a. Determine if an 8051 in mode 1 can communicate with an 8051 in mode 3.20207m

    Module 5: External Communication Interface

    Determine if an 8051 in mode 1 can communicate with an 8051 in mode 3.

    View this question on its own page →

    CopySearch GoogleAsk AI

    Worked Solution

    Can 8051 Mode 1 communicate with Mode 3?

    No, not directly without adaptation.

    • Mode 1: 10-bit frame: 1 start + 8 data + 1 stop, variable baud via Timer1.
    • Mode 3: 11-bit frame: 1 start + 8 data + 1 programmable 9th bit (TB8/RB8) + 1 stop, variable baud.

    Receiver in Mode 3 expects 9th bit; transmitter in Mode 1 does not send it (or sends stop as 9th). Baud rates may match but frame mismatch causes framing errors and RB8 misinterpretation. Multiprocessor bit SM2 handling also differs.

    If forced: Mode 3 receiver can be configured to ignore 9th bit (SM2=0, and software ignores RB8), and Mode 1 transmitter's stop bit will be sampled as 9th bit. With SM2=0, communication can succeed with 8 data bits but 9th bit is garbage. For robust communication, both sides must be same mode (both Mode 1 or both Mode 3). Mixed mode is unreliable and not recommended.

15. Q3b. Character transmission can be done by using a time delay greater than the character time before moving a new byte to SBUF. Explain why character reception must use an interrupt flag if all characters are to be received.20207m

    Module 5: External Communication Interface

    Character transmission can be done by using a time delay greater than the character time before moving a new byte to SBUF. Explain why character reception must use an interrupt flag if all characters are to be received.

    View this question on its own page →

    CopySearch GoogleAsk AI

    Worked Solution

    Why Reception Must Use Interrupt Flag

    Transmission can use time delay because transmitter controls timing; SBUF loaded after >character time ensures previous byte finished.

    Reception is asynchronous – sender timing unpredictable, start bit arrives anytime. Polling by delay may miss bytes because:

    1. If polling period > character time, bytes are overwritten (overrun). 8051 double-buffering means second byte overwrites before RI flags.
    2. Flag RI is set at middle of stop bit, accurate timing; polling delay not synchronized to start bit, so sampling may miss.
    3. Continuous back-to-back characters require detection of each stop→start transition; interrupt on RI ensures every byte captured and software can read SBUF before next. Hence reception must check RI flag (poll or interrupt) not blind delay.
16. Q4a. Explain the interfacing of Bluetooth and Zigbee with the 8051 microcontroller.20207m

    Module 5: External Communication Interface

    Explain the interfacing of Bluetooth and Zigbee with the 8051 microcontroller.

    View this question on its own page →

    CopySearch GoogleAsk AI

    Worked Solution

    Interfacing Bluetooth and Zigbee with 8051

    Both use UART (RS232 level via MAX232 or 3.3V logic via voltage divider) on P3.0/P3.1.

    Bluetooth (e.g., HC-05):

    • VCC 5V/3.3V, GND, TX→8051 RxD (P3.0), RX→8051 TxD (P3.1) via divider, EN/KEY for AT mode.
    • Config 9600 baud (TH1=0FDH). Send AT commands via serial: AT+NAME, AT+PIN.
    • Data: Write SBUF, poll TI; receive interrupt RI. Add 3.3V regulation if needed.

    Zigbee (e.g., XBee S2):

    • Pins: VCC 3.3V, GND, DIN→TxD, DOUT→RxD, plus CTS/RTS optional.
    • Uses 802.15.4, mesh. Config via X-CTU: PAN ID, Channel, MY/DH/DL addresses.
    • UART frames same as above; API vs AT mode. Baud 9600/115200.
    • For 5V 8051, level shift 5V→3.3V on DIN.

    Software common: Initialize serial mode 1, Timer1 baud, then MOV SBUF,A transmit to module; module handles wireless to peer. Receive bytes via ISR and process.

17. Q4b. Explain the various external interrupt signals in 8051.20207m

    Module 2: The 8051 Architecture

    Explain the various external interrupt signals in 8051.

    View this question on its own page →

    CopySearch GoogleAsk AI

    Worked Solution

    External Interrupt Signals in 8051

    • \overline{INT0} (P3.2) & \overline{INT1} (P3.3): Active-low inputs. Trigger mode selectable via IT0/IT1 in TCON: ITx=0 level-triggered (low holds interrupt), ITx=1 edge-triggered (falling edge). Flags IE0/IE1 set; auto-cleared for edge after ISR.
    • Vector addresses: INT0=0003H, INT1=0013H.
    • Enable: EX0/EX1 in IE, global EA.
    • Priority: PX0/PX1 in IP.
    • Usage: Connect external device with pull-up, drive low pulse >1 machine cycle for edge; hold low until serviced for level.

    Also serial and timer interrupts are internal but often listed.

18. Q5a. Explain the overview of 8051 family.20207m

    Module 1: Fundamentals of Microprocessors

    Explain the overview of 8051 family.

    View this question on its own page →

    CopySearch GoogleAsk AI

    Worked Solution

    Overview of 8051 Family

    MCS-51 launched by Intel 1980. Members: 8051 (4KB ROM,128B RAM), 8052 (8KB/256B + T2), 8031 (0KB ROM-less), 8751 (EPROM), AT89C51 (Flash), AT89S52 etc. Derivatives from Philips, Atmel, NXP, Silicon Labs. Core: 8-bit CPU, 32 I/O, 2 timers, 5 interrupts, 1 UART, 64K program/data, 40-pin. Extensions: 80C51 CMOS, low-power, more timers, ADC, CAN. Modern: 8051 IP core still widely used in SoCs.

19. Q5b. List and explain the important processors used in embedded systems.20207m

    Module 1: Fundamentals of Microprocessors

    List and explain the important processors used in embedded systems.

    View this question on its own page →

    CopySearch GoogleAsk AI

    Worked Solution

    Important Processors in Embedded Systems

    • 8051 family (Intel/MCS-51): 8-bit control, cheap, widespread for appliances.
    • AVR (ATmega): RISC, Arduino, low-power.
    • PIC (Microchip): Wide range, industrial.
    • ARM (Cortex-M0/M3/M4): 32-bit, high-performance, phones, RTOS.
    • MSP430 (TI): Ultra-low-power for battery/IoT.
    • RISC-V: Open-source, emerging.
    • DSPs (TI C2000): Signal processing.
    • SoCs (ESP32): WiFi/BT + MCU.

    Selection depends on performance, power, cost, peripherals, tool chain.

20. Q6a. Explain the oscillator circuit and timing of the 8051 microcontroller.20206m

    Module 2: The 8051 Architecture

    Explain the oscillator circuit and timing of the 8051 microcontroller.

    View this question on its own page →

    CopySearch GoogleAsk AI

    Worked Solution

    Oscillator Circuit & Timing – see Q121

    Crystal between XTAL1/2 with internal inverter, 30pF caps. Generates Fosc, divided by 12 for machine cycle (6 states ×2). ALE 1/6 Fosc, PSEN, timers, baud derived. 12MHz →1µs MC; 11.0592MHz →1.085µs ideal for baud. Reset needs 2 cycles high.

21. Q6b. Explain the functions of the following pins: (i) ALE (ii) \overline{PSEN} (iii) \overline{EA} (iv) RST20208m

    Module 2: The 8051 Architecture

    Explain the functions of the following pins:
    (i) ALE
    (ii) $\overline{PSEN}$
    (iii) $\overline{EA}$
    (iv) RST

    View this question on its own page →

    CopySearch GoogleAsk AI

    Worked Solution

    Functions of ALE, \overline{PSEN}, \overline{EA}, RST

    • ALE (30): Address Latch Enable – active-high pulse at 1/6 Fosc to latch low address A0-A7 from P0 into external latch (74LS373). Demultiplexes address/data. Also used as \overline{PROG} for Flash programming.
    • \overline{PSEN} (29): Program Store Enable – active-low output, reads external program memory (ROM) when CPU fetches outside internal. Connects to OE of external EPROM/Flash. Inactive high when executing internal.
    • \overline{EA}/VPP (31): External Access – input. EA=1 → fetch internal first (0000-0FFFH) then external after; EA=0 → all fetches external, 0H vectors external. Also VPP 21V for EPROM programming.
    • RST (9): Reset – active-high input, hold >2 machine cycles (>1µs) to reset PC=0000H, SP=07H, ports high, etc. Needs RC (10µF+8.2k) power-on.
22. Budget App•POCKETLY

    Pocketly on Android

    Log daily food, travel, and hostel expenses instantly. Set monthly spending limits and see where your money goes without complex spreadsheets.

    Install Pocketly
23. Q7a. Explain the alternate functions of port 0, port 2 and port 3.20206m

    Module 2: The 8051 Architecture

    Explain the alternate functions of port 0, port 2 and port 3.

    View this question on its own page →

    CopySearch GoogleAsk AI

    Worked Solution

    Alternate Functions of Port 0, Port 2, Port 3

    • Port 0 (AD0-AD7): Normal quasi-I/O with pull-ups, but when external memory accessed, becomes multiplexed low address/data bus latched by ALE. Open-drain, needs external pull-up for input.
    • Port 2 (A8-A15): Quasi I/O; alternately high address byte for external memory (stable during data phase). Does not need latch.
    • Port 3 (8 alternates as Q1): P3.0 RxD, P3.1 TxD, P3.2 INT0, P3.3 INT1, P3.4 T0, P3.5 T1, P3.6 WR\ (data write strobe), P3.7 RD\ (data read). Selected when corresponding SFR bit enables function; else acts as I/O.
24. Q7b. Explain how bit addressing is distinguished from byte addressing in the 8051 microcontroller.20208m

    Module 2: The 8051 Architecture

    Explain how bit addressing is distinguished from byte addressing in the 8051 microcontroller.

    View this question on its own page →

    CopySearch GoogleAsk AI

    Worked Solution

    Bit vs Byte Addressing in 8051

    • Byte addressing: Access entire 8-bit byte via direct or indirect address (00-7FH RAM, 80-FFH SFRs, etc.) e.g., MOV A,30H loads 8 bits; address granularity is byte.
    • Bit addressing: Access single bit individually via bit address. 8051 has 211 bit addresses: 128 in RAM 20H-2FH (bits 00H-7FH where bit address = byte_address_offset×8 + bit) and 87 in SFRs ending 0/8H (e.g., PSW.7=CY, P1.0). Instructions: SETB bit, CLR bit, MOV C,bit, JB bit,rel. Bit address distinguishes via 8-bit bit address encoding vs byte direct. Example SETB 00H sets RAM 20H.0, SETB P1.0 vs MOV P1,#01H byte.
25. Q8a. Explain the register addressing mode and direct addressing mode in 8051.20208m

    Module 3: Instruction Set and Programming

    Explain the register addressing mode and direct addressing mode in 8051.

    View this question on its own page →

    CopySearch GoogleAsk AI

    Worked Solution

    Register & Direct Addressing Mode – 8051

    • Register Addressing: Operand in R0-R7, A, B. Encoding selects register via 3-bit field within opcode, e.g., INC R3, ADD A,R2, MOV A,R5 – fast, 1 byte.
    • Direct Addressing: 8-bit direct address follows opcode, accesses internal RAM 00-7FH or SFR 80-FFH directly, e.g., MOV A,30H load from RAM location 30H, MOV 30H,A, MOV P1,80H. Note: Direct accesses SFR when 80-FFH range; via indirect @R0 that accesses upper RAM not SFR. 2 bytes. Direct can also address bit as second byte.
26. Q8b. Explain the data transfer instructions and arithmetic instructions with few examples.20206m

    Module 3: Instruction Set and Programming

    Explain the data transfer instructions and arithmetic instructions with few examples.

    View this question on its own page →

    CopySearch GoogleAsk AI

    Worked Solution

    Data Transfer & Arithmetic Instructions – Examples (as Q148)

    Data Transfer:

    • MOV A,#25H (immediate→A)
    • MOV 30H,A (A→direct)
    • MOV A,@R0 (indirect)
    • MOV DPTR,#1000H
    • MOVC A,@A+DPTR (table)
    • MOVX A,@DPTR (external)
    • PUSH ACC, POP B

    Arithmetic:

    • ADD A,R0 (A+=R0, CYOV)
    • ADDC A,#10H with carry
    • SUBB A,R1
    • INC DPTR
    • MUL AB, DIV AB, DA A (decimal adjust).

    Example program snippet adding two arrays etc.