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MICROPROCESSORSWhich member of MCS-51 family contains an internal ROM of 0 KB? (i) 8051 (ii) 8951 (iii) 8031 (iv) None of the above20232mMICROPROCESSORSWhich output control signal is activated after every six oscillator periods while fetching the external program memory and almost remains high during internal program execution? (i) ALE (ii) \overline{PSEN} (iii) \overline{EA} (iv) All of the above20212mMICROPROCESSORSWhich serial modes possess the potential to support the multi-processor type of communication? (i) Modes 0 & 1 (ii) Modes 1 & 2 (iii) Modes 2 & 3 (iv) All of the above20202mMICROPROCESSORSWhich of the following control signal becomes high in T1 clock cycle and remains deactivated in T2 clock cycle and onwards? (i) ALE (ii) \overline{PSEN} (iii) \overline{EA} (iv) All of the above20232m
PreviousWhich operation is performed by stack pointer during its incremental phase? (i) Push (ii) Pop (iii) Return (iv) All of the aboveNextWhat kind of triggering configuration of external interrupt intimate(s) the signal to stay low until the generation of subsequent interrupt? (i) Edge-triggering (ii) Level triggering (iii) Both (i) and (ii) (iv) None of the above
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