Which of the following control signal becomes high in T1 clock cycle and remains deactivated in T2 clock cycle and onwards? (i) ALE (ii) \overline{PSE

Question

**Which of the following control signal becomes high in T1 clock cycle and remains deactivated in T2 clock cycle and onwards?**
(i) ALE
(ii) $\overline{PSEN}$
(iii) $\overline{EA}$
(iv) All of the above

Accepted Answer

**Answer: (i) ALE**

**Explanation:** ALE (Address Latch Enable) is the 8051 output that pulses high during state T1 of each machine cycle to latch the low-byte address (P0) into an external latch (74LS373). It then goes low and remains low (deactivated) during T2 and onwards for that cycle, while \overline{PSEN} (active-low) goes low during the fetch phase. \overline{EA} is an input. So the signal that becomes high in T1 and stays deactivated thereafter is ALE.

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