Daisy-Chain Priority Interrupt

A method to resolve simultaneous interrupt requests and assign priority by hardware wiring rather than polling software.

1. Principle

All interrupt sources are serially connected (daisy-chained) on an Interrupt Acknowledge (INTA) line from CPU.

• Higher priority device is placed electrically nearer to CPU.
• When CPU acknowledges interrupt (INTA=1), signal propagates sequentially.
• First requesting device blocks propagation and places its vector address on bus; lower priority devices never see INTA.

2. Hardware Structure

CPU INTR ← OR of all INT requests
CPU INTA → Device0 PI → Device1 PI → Device2 PI → ...
           Device0 PO ─┘  Device1 PO ─┘
(Device with PI=1, PO=0 handles interrupt)

Each interface contains:

• Interrupt flip-flop (sets when device requests),
• PI (Priority In) / PO (Priority Out) logic: PO = PI · ¬(INT_request),
• Vector address generator / tri-state buffer enabled only when PI·INT·INTA.

3. Operation Sequence

1. One or more devices set INT.
2. CPU finishes current instruction, checks INTR, if enabled pushes PC/PSW, disables further interrupts, asserts INTA.
3. INTA ripples: Device0 check: if it requested, it clears its flag, asserts PO=0 (blocks chain), puts VAD on data bus; CPU reads vector → ISR address.
4. If Device0 not requesting, it passes PO=1 (=PI) to next device; same logic repeats.
5. ISR at end executes RETI, restores state.

4. Priority Assignment

Physical order = priority. No extra encoder needed. Typical max $5\text{-}8$ devices per chain; longer chain adds propagation delay (~10-20 ns/gate).

5. Advantages / Disadvantages

Advantages:

• Simple, cheap, scalable, no polling overhead.
• Automatic priority resolution in one INTA cycle.
• Vectored interrupt possible per device.

Disadvantages:

• Priority fixed by wiring (re-cabling to change).
• Chain delay limits number of devices.
• Single fault breaks chain (can be solved with open-collector / bypass cap).
• Starvation of low priority devices.

6. vs Other Methods

• Polling: Software tests each flag sequentially - slower but flexible.
• Parallel priority encoder / Arbiter: Faster, programmable priority but more hardware.

Daisy-chain is widely used in e.g. 8085 RST 7.5/6.5/5.5, VME bus, and legacy peripheral chains.