Daisy Chaining Priority (Daisy Chain Interrupt Arbitration) [7M]

Context: When multiple I/O devices share single interrupt line ($INTR$) to CPU, need to decide priority if several request simultaneously. Daisy chain is hardware serial priority method.

Structure:

Devices connected in series like chain. CPU's Interrupt Acknowledge ($INTA$ / $BG$ - Bus Grant) propagates serially.

CPU INTA (BG) ----> Device1 --BGout--> Device2 --BGout--> Device3 ---->
         ^           |                 |                 |
         +-----------+-----------------+-----------------+---- INTR (wired-OR) to CPU

Each device has Interrupt Request (IR) and Priority In / Priority Out.

• Device generates $IR$ when needs service.
• $INTR = IR1\ OR\ IR2\ OR\ ...$ -> to CPU.
• CPU responds with $INTA=1$ (daisy chain enable) when ready to serve.

Logic per device:

if IR=1 and PriorityIn=1  =>  PriorityOut=0, acquire bus, put vector on bus, block downstream
else PriorityOut = PriorityIn

Propagation: $PriorityIn_{i+1} = PriorityOut_i = PriorityIn_i \cdot \overline{IR_i}$

Thus highest physical position gets highest priority (closest to CPU). Need to insert higher priority devices nearer CPU.

Operation Sequence:

1. Device 2 and 3 request simultaneously: $IR2=IR3=1$, $INTR=1$ -> CPU finishes current instruction, saves PC/PSW, disables further interrupts.
2. CPU asserts $INTA$. Device1 $PriorityIn=1$ but $IR1=0$, so passes $PriorityOut=1$ to Device2.
3. Device2 sees $PriorityIn=1$ and $IR2=1$ -> blocks propagation ($PriorityOut=0$), puts its interrupt vector address on data bus, clears IR.
4. Device3 sees $PriorityIn=0$ -> cannot respond even though $IR3=1$, waits for next INTA.
5. CPU reads vector, jumps to ISR for Device2.

Advantages:

• Simple: 1 INTR + 1 INTA lines, no encoder. Easy to add devices (plug into chain).
• No separate priority encoder. Software can poll via vector.

Disadvantages:

• Priority fixed by position - re-wiring needed to change priority.
• Propagation delay linear in $n$ - limits number of devices ($t_{ack}= n \cdot t_{gate}$). Fail in one device breaks chain unless bypass logic.
• Starvation of low priority devices.

Variants:

• Parallel priority encoder (8259 PIC) solves delay via hardware priority resolver.
• Polling alternative: CPU polls each device SR via software (flexible priority but slower).

Example use: Unibus, Intel Multibus Bus Grant ($BPRN/BPRO$), SPI devices with daisy chain.

Contrast: Independent request (each device has separate IR line) allows programmable priority but needs $n$ lines. Daisy chain trades flexibility for wiring simplicity.