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Module 2: x86 Architecture, CPU Control, I/O, Memory System Design

20167m

Write short notes on the following:

  • (a) Shift instructions
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Shift Instructions [7M]

Shifts move bits left/right within register/word. Crucial for scaling (multiply/divide by 2k2^k), bit manipulation, floating point normalization, I/O serialization.

Types:

1. Logical Shift:
Vacated bits filled with 0. Used for unsigned numbers.

  • SHL / LSL Logical Shift Left: C <- b_{n-1} ... b0 <- 0 . E.g. 01010111 <<1 = 10101110, carry out =0. Equivalent to *2 (unsigned).
  • SHR / LSR Logical Shift Right: 0 -> b_{n-1} ... b0 -> C. E.g. 10110011 >>2 = 00101100. Equivalent to unsigned /4.
    Example x86: SHL AX,1 , SHR BX, CL (CL = count).

2. Arithmetic Shift:
Preserves sign (for signed 2's complement).

  • SAL = SHL (same for left).
  • SAR Arithmetic Shift Right: vacated left bits filled with sign bit (MSB replicated). 1XXXX -> 11XXX. E.g. 11100100 (-28) SAR 1 = 11110010 (-14) correctly divides by 2. 01000000 (64) SAR1 =00100000 (32). LSR would give incorrect negative.
  • Arithmetic left shift: sign bit not replicated; overflow checked via V flag if sign changes.

3. Circular / Rotate (no loss):
Bits that fall off are wrapped around.

  • ROL Rotate Left: b_{n-1} -> b0 and -> Carry. ROR opposite. E.g. 10001111 ROL1 =00011111.
  • RCL/RCR Rotate through Carry: Includes carry in loop (9-bit rotation for 8-bit reg). Used for multi-precision shifts: RCL propagates carry across words.
  • Used for cryptography, bit extraction.

Hardware: Barrel shifter - combinational n×log⁡nn \times \log n mux network can shift any kk (0..n-1) in single cycle vs sequential shift register (kk cycles).

Applications & Examples:

  • Multiplication/Division by power of 2: X *8 = SLL X,3 much faster than MUL. X/8 = SAR X,3 (signed).
  • Example 8-bit: 00001101 (13) <<2 =00110100 (52)=13*4 .
  • Multiplication of 14∗514 *5: 14 <<2 +14 = 56+14=70 without multiplier.
  • Normalization: Floating addition requires align exponents via right shift of mantissa.
  • Field extraction: MOV AL,mask; AND; SHR.

Flags: Shift updates C (last bit out), Z,S,P, arithmetic checks V/O.

Summary table:

Type Fill Use
LSL/SHL 0 Unsigned *2k2^k
LSR 0 Unsigned /2k2^k
ASR/SAR sign Signed /2k2^k
ROL/ROR wrap Rotate

Modern ISAs provide SHL, SHR, SAR, ROL, ROR, RCL, RCR, SHLD/SHRD (double precision shift).

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