Short Note: RISC and CISC Processor (7 Marks)

CISC – Complex Instruction Set Computer (e.g., Intel x86, VAX, 68k):

• Large instruction set: 100-300+ instructions, many addressing modes (12-24), variable length (1-12 bytes)
• Complex instructions do multi-step operations (e.g., MUL 2:3,5:2 memory-to-memory, string copy)
• Microprogrammed control – instructions decoded into micro-ops
• Memory-to-memory operations allowed, few registers (8-16)
• Compact code (high code density), but variable CPI, long cycles, complex compiler to use exotic instructions.
• Aims to reduce semantic gap.

RISC – Reduced Instruction Set Computer (e.g., ARM, MIPS, RISC-V, PowerPC):

• Small set (~30-50 core instructions), simple fixed length (4 bytes), limited addressing modes (register + displacement)
• Load/Store architecture – only LOAD/STORE access memory, ALU ops only on registers
• Large register file (32+ registers), hardwired control (fast)
• CPI ≈1 with deep pipelining, easy to pipeline/superscalar
• Relies on optimizing compiler, more code size but higher performance per clock (MIPS)
• Example: ADD R1,R2,R3 all registers, 3-operand.

Comparison:

Aspect	RISC	CISC
Instructions	Few, simple	Many, complex
Length	Fixed	Variable
Addressing	Few (2-3)	Many (12+)
Registers	Many (32+)	Few (8-16)
Memory access	Load/Store only	Memory can be operand
Control	Hardwired	Microprogrammed
CPI	~1	>1 variable
Code size	Larger	Smaller
Pipeline	Efficient	Difficult

Modern hybrid: x86 internally translates CISC → RISC micro-ops; ARM adds some CISC features – distinction blurring.