I/O Device Interfaces [7M]

Need: I/O devices are electromechanical / heterogeneous in speed (keyboard ~10 Hz, disk ~100 MB/s), word format, voltage levels, timing vs CPU. Direct connection impossible. I/O Interface / I/O Module acts as mediator between CPU/system bus and peripheral.

Block Diagram:

CPU <--> System Bus (Address/Data/Control) <--> I/O INTERFACE <--> Peripheral
                                                | - Address decoder
                                                | - Data Buffer Register (DBR)
                                                | - Status/Control Registers
                                                | - Control logic + timing
                                                | - Interrupt/DMA logic

Functions:

1. Address decoding & selection: Decodes address bus, responds only to its port addresses (memory-mapped or isolated I/O). Chip select.
2. Synchronization / Speed matching: Buffers data, handshake signals (READY, STROBE, ACK) to match slow device with fast CPU.
3. Data format conversion: Serial <- -> Parallel (UART), analog-digital, code conversion (ASCII).
4. Error detection: Parity, CRC; reports via status register.
5. Timing & control: Generates device-specific control signals (READ, WRITE, SEEK).

Registers (visible to CPU):

• Data Register (DR / DBR): Holds data to be transferred.
• Status Register (SR): Flags - DONE/READY, BUSY, ERROR, INTERRUPT. CPU polls or interrupt based.
• Control/Command Register (CR): CPU writes to start operation, set mode (read/write), enable interrupt.

Example x86: IN AL, PORT reads status/data, OUT PORT, AL writes command.

Types of Interfaces:

1. Programmed I/O interface: e.g. Intel 8255 PPI (Parallel Peripheral Interface) - three 8-bit ports, Mode 0/1/2. CPU polls BUSY bit.
2. Interrupt-driven interface: e.g. 8259 PIC + interface that raises INTR when DONE.
3. DMA interface: Includes DMA controller logic that can become bus master.
4. Serial interface: Intel 8251 USART, 16550 UART - converts parallel to serial with start/stop bits, baud rate generator.
5. Modern: USB controller, SATA, PCIe - complex interfaces with FIFO, protocol engines.

Design example - Parallel Interface:

Address decode -> when IO/M=1 and Addr = 40H, select. Data buffer isolated via tri-state. Handshake: CPU writes data to DR, sets CONTROL START=1, peripheral asserts ACK when taken, interface sets STATUS READY=1.

Isolated vs Memory-mapped:
Isolated uses IN/OUT and separate control line; memory-mapped maps registers to memory addresses, uses MOV instructions, simplifies decoding but consumes memory space.

Conclusion: Interface provides port abstraction so CPU sees uniform register interface regardless of physical device heterogeneity.