Instruction Set Architecture (ISA) [7M]

Definition: ISA is abstract interface between hardware and software - the functional appearance of processor as seen by assembly/machine programmer and compiler. It defines what CPU does, not how. Part of computer architecture (ISA + organization + hardware).

ISA is contract: software written to ISA runs on any implementation (Intel x86, ARMv8, RISC-V).

Key Components:

1. Instruction Format & Encoding:

• Length: Fixed (RISC: 32-bit) vs Variable (CISC: x86 1-15B)
• Fields: | Opcode | Addressing mode | Operand(s) |
• Example x86: opcode + ModR/M + SIB + displacement + immediate
• Number of addresses: 0-addr (stack), 1-addr (accumulator), 2-addr, 3-addr (RISC: ADD R1,R2,R3)

2. Instruction Types / Operations:

• Data transfer: MOV, LOAD, STORE, PUSH
• Arithmetic/Logic: ADD, SUB, AND, OR, SHL
• Control: JMP, CALL, RET, BRANCH (BEQ, BNE)
• FP / SIMD / String

3. Data Types & Operand Types:

• Integer (8/16/32/64), floating point (IEEE 754), BCD, char, vector. Word size.
• Registers, memory, immediate, stack.

4. Addressing Modes:
Direct, indirect, register, immediate, indexed, auto-increment, PC-relative.
Determines how effective address calculated: $EA = R + offset$.

5. Registers:

• Visible: GPRs, FP registers, vector, flags/PSW, PC, SP, control regs.
• Number: e.g. x86_64: 16 GPRs, ARM: 31, RISC-V: 32. Affects compiler.

6. Memory Model & Endianness:

• Address space, alignment (aligned vs unaligned), little/big endian (x86 little).

7. Control & Execution Model:

• Fetch-decode-execute, pipelining effects, exception/interrupt handling, privilege levels (user/supervisor), virtual memory support.

Design Styles:

• CISC (Complex): Many addressing modes, variable length, microcoded, few registers, memory-to-memory ops. Example: x86. ADD M, R. Code dense.
• RISC (Reduced): Load/Store architecture, fixed length, many registers (32+), simple modes, hardwired, pipeline optimized. Example: ARM, MIPS, RISC-V. LOAD R1,M; ADD R3,R1,R2; STORE R3,M.

ISA Design Tradeoffs:
Orthogonality, completeness, regularity vs code size, implementation complexity, performance. Measured by CPI, Instruction count, Time = IC * CPI * Cycle.

Example RISC-V 32I base: 47 instructions: 6 formats (R/I/S/B/U/J). Very regular.

Importance: ISA determines compiler target, OS portability, performance and power envelope. x86 dominates desktop/server via binary compatibility; ARM dominates mobile via power-efficient ISA.

Diagram: Software (HLL -> Compiler -> ASM) -> ISA Boundary -> Hardware (microarchitecture: pipeline, cache, ALU).