Architecture of x86 Processors

x86 (Intel 8086 -> Pentium -> x64) is a CISC, Little-endian, Register-Memory architecture, evolved to 16/32/64-bit with backward compatibility.

A. Overall Architecture (8086 classic - foundation)

• Two units: BIU (Bus Interface Unit) and EU (Execution Unit) with 6-byte prefetch queue enabling pipelined fetch-execute.
  • BIU: segment registers, IP, address generation (Segment×16 + Offset = 20-bit physical), bus control, prefetch.
  • EU: ALU, control, registers - decodes & executes from queue.
• Modern x86: Superscalar, out-of-order, deep pipeline (14-19 stages), micro-ops translation, multiple cores, caches L1/L2/L3, branch predictor, MMU with TLB.

B. Registers

Category	Registers	Details
General Purpose (GPR)	AX,BX,CX,DX (16-bit, split AH/AL) -> extended to EAX,EBX,ECX,EDX (32-bit), RAX... (64-bit)	AX=accumulator, BX=base, CX=count, DX=data. Also 8 new R8-R15 in x64
Pointer/Index	SP,BP,SI,DI -> ESP,EBP,ESI,EDI -> RSP,RBP,RSI,RDI	SP=Stack Pointer, BP=Base Pointer, SI=Source Index, DI=Dest Index
Segment	CS,DS,SS,ES,FS,GS (16-bit)	CS:Code, DS:Data, SS:Stack, ES:Extra. In protected mode hold selectors (index to GDT). Real mode: Segment<<4 + Offset
Instruction Pointer	IP -> EIP -> RIP	Holds offset of next instruction in CS
Flags	FLAGS/EFLAGS/RFLAGS (16/32/64)	CF,ZF,SF,OF,PF,AF,IF,DF,TF - status & control
Control/System	CR0-CR4, DR0-DR7, GDTR,LDTR,IDTR,TR, MSRs	Paging (CR3=page table base), protection
Floating/SIMD	x87 stack ST0-7, MM0-7, XMM0-15, YMM/ZMM	For FP and AVX

C. Addressing Modes

x86 has most varied modes:

1. Immediate: MOV AX, 1234H - operand in instruction
2. Register: ADD AX, BX - operand in register
3. Direct / Absolute: MOV AX, [5000H] - offset given
4. Register Indirect: MOV AX, [BX] ; [SI], [DI], [BP] (default SS for BP)
5. Based Indexed: MOV AX, [BX+SI] , [BP+DI]
6. Based Indexed + Displacement: MOV AX, [BX+SI+8] , MOV AX, [500H+BX]
7. Relative (PC): JMP Label - IP + disp (for branches)
8. Implied: AAA, STC - operand implied.
9. Segment Override: MOV AX, ES:[BX] - explicit segment.

Effective Address = Base + Index*Scale(1,2,4,8) + Displacement (SIB byte in 32/64-bit) then Physical = SegmentBase + EA (real mode) or via paging.

D. Instruction Format (Variable length, 1-15 bytes)

Classic x86 is variable-length CISC:

[Prefixes: 0-4B] [Opcode:1-3B] [ModR/M:1B] [SIB:1B] [Displacement:0/1/2/4B] [Immediate:0/1/2/4B]

• Prefixes: LOCK, REP, segment override, operand-size override (66H), address-size, REX (64-bit)
• Opcode: e.g., 88H=MOV r/m8,r8, 03H=ADD r,r/m
• ModR/M: mod(2)|reg/op(3)|r/m(3) selects addressing mode and registers.
• SIB: scale(2)|index(3)|base(3) for complex [base+index*scale]
• Example: ADD EAX, [EBX+ESI*4+1000H] encoded as ~6 bytes: 03 84 B3 00 10 00 00

Protected/Long mode adds REX prefix for R8-R15 and 64-bit operand size.

Evolution: 8086 (16-bit, 1MB, 29k transistors) -> 80286 (protected) -> 80386 (32-bit paging) -> Pentium (superscalar) -> x86-64 (AMD64, 64-bit). Modern x86 translates CISC instructions to RISC-like micro-ops (uOps) for OOO execution while preserving CISC ISA.