Answer: (iii) Sign flag is 0

Explanation: In 8085, JP = Jump if Plus (positive) - branches when Sign flag S = 0 (result positive, MSB =0). JM jumps if S=1 (minus). JZ/JNZ test Zero, JC/JNC test Carry, JP/JM test Sign, JPE/JPO test Parity. JP specifically: if S=0 then PC←address. So option (iii) Sign flag 0.

Answer: (ii) LDAX

Explanation: In 8085, LDAX B/D (Load Accumulator indirect) copies content of memory location whose 16-bit address is in register pair B-C or D-E into accumulator using register-indirect addressing. STAX does the opposite (A → memory). LDA is direct 16-bit address. Hence LDAX uses register indirect.

Answer: (iv) 48

Explanation: 8051 MUL AB multiplies unsigned 8-bit A × B → 16-bit product in B:A (B high, A low). Execution time is 4 machine cycles. At 12 oscillator periods per machine cycle (traditional 8051), 4×12 = 48 oscillator periods. Hence option (iv) 48. (Some CMOS variants 6T mode differ, but exam expects 48.)**

Answer: (iv) 48

Explanation: Same as Q30 - MUL AB takes 4 machine cycles = 4×12 = 48 oscillator periods (12 clocks per machine cycle on standard 8051). Product placed in B (high byte) : A (low byte). Flags: OV set if product >255, CY cleared.

Answer: (iii) CPL

Explanation: CPL A (Complement Accumulator) does A = ~A (ones complement) and affects no flags. CLR A clears A to 0 and also no flags but not complement. SETB sets a bit flag. Complement operations in 8051 (CPL A, CPL C, CPL bit) are defined to leave PSW flags unchanged (except CPL C complements Carry). For single-operand complement of accumulator without flag change, CPL A is correct.

Answer: (iv) It performs memory write operation

Explanation: PUSH B (push register B onto stack) increments SP then writes B to internal RAM at [SP]. So it is a memory write, not read, not arithmetic. It takes 2 machine cycles (24 oscillator periods) on 8051, not single. It uses direct addressing for B but stack operation is indirect via SP. Hence only (iv) is true.

Answer: (i) Arrays

Explanation: Indexed addressing mode (e.g., MOVC A,@A+DPTR or MOVC A,@A+PC, and MOVX) forms effective address as base + index, ideal for accessing tables/arrays, look-up tables, and string data. It is not primarily for stack or arithmetic.

Answer: (i) Jump if no carry, jumps if CY=0

Explanation: JNC = Jump if No Carry. In 8051, JNC rel : if PSW.CY =0 then PC←PC+offset, else next instruction. JC jumps if CY=1. Hence (i) is correct.

Answer: (iii) -128 to 127 bytes

Explanation: Relative addressing in 8051 (SJMP, conditional jumps JC/JNC, JZ/JNZ, DJNZ, CJNE) uses an 8-bit signed offset added to PC after fetching the jump instruction. 8-bit 2's complement range is -128 to +127 bytes relative to the first byte of the next instruction (PC after fetch). Some textbooks quote -128 to +127 relative to current PC. Hence the range is -128 to +127.

Answer: (ii) Send the data to the stack, copy the data from the stack

Explanation: PUSH sends/copies source byte to stack (write, SP++), POP copies data from stack to destination (read, SP--). Option (ii) states PUSH = to stack, POP = from stack, which is correct. Option (i) reverses them.

Answer: (i) DJNZ

Explanation: DJNZ = Decrement and Jump if Not Zero: DJNZ direct/Reg, rel → decrement operand; if result ≠0 jump. AJMP is absolute jump, CJNE is compare and jump if not equal, NOP is no operation.

Answer: (ii) Assembler

Explanation: Assembler translates assembly mnemonics directly to machine code (opcode + operand). Compiler translates high-level language to machine code, text editor edits source, debugger tests execution.

Indexed & Relative Addressing in 8051

1. Indexed Addressing: EA = Base + Index. Base is DPTR or PC, index is Accumulator. Instructions: MOVC A,@A+DPTR and MOVC A,@A+PC. Used for table look-up, e.g., fetch byte from code memory table whose base address in DPTR plus offset in A. Example:

MOV DPTR,#TABLE
MOV A,R2 ; offset 2
MOVC A,@A+DPTR ; A = TABLE[2]
TABLE: DB 10H,20H,30H

Also MOVX with DPTR indirect is variant.

2. Relative Addressing: EA = PC + signed 8-bit offset (2's complement, -128 to +127). Used by jumps: SJMP rel, JC/JNC/JZ/JNZ/DJNZ/CJNE rel. Offset relative to next instruction's first byte. Example: SJMP LOOP assembles to -X offset. Allows relocatable code and short jumps within 256-byte range.

Program: Convert odd-parity bytes to even-parity (bit7 is parity bit)

Odd parity means total 1s (including bit7) odd; even parity means total 1s even. Convert by toggling bit7 if needed.

ORG 0000H
MOV R0,#30H ; source array start
MOV R1,#40H ; destination or same buffer
MOV R2,#10H ; count = 16 bytes example
LOOP: MOV A,@R0
      MOV C,P   ; P = parity flag (PSW.0) =1 if odd parity in A
      ; For odd parity bytes, P=1, for even P=0
      ; We want to ensure even parity in result (including bit7)
      ; If current parity is odd (P=1) with current bit7, then need to toggle bit7
      ; Actually if accumulator currently has odd parity (P=1), then total 1s odd -> to make even, flip bit7
      JNB P,NEXT ; if already even, keep bit7
      CPL ACC.7  ; invert parity bit
NEXT: MOV @R1,A
      INC R0
      INC R1
      DJNZ R2,LOOP
      SJMP $
END

Logic: P flag reflects parity of A. For each byte, if P=1 (odd), complement bit7 to make even parity; if P=0 leave. This swaps odd→even. Alternative sequence: ANL A,#7FH to clear bit7, then set bit7 to make even; but above correctly toggles.

Programming & Debugging Tools for 8051

• Assembler (A51) & Compiler (C51/Keil, SDCC): Translate assembly/C to hex.
• Simulator (Keil µVision, Proteus): Functional simulation, register/memory view, breakpoints.
• Emulator (ICE, JTAG): In-circuit emulation with real hardware timing.
• Programmer/Burner: EPROM/Flash programmer (e.g., TL866) with \overline{EA}/ALE programming mode.
• Debugger: Single-step, watch windows, trace, logic analyzer, oscilloscope for timers/serial.
• IDEs: Keil, IAR, Eclipse with 8051 plugin.
• Development boards: With LEDs, switches, LCD, serial, for testing.

Program Development Tools (Microprocessor/Microcontroller)

• Editor/IDE: Keil µVision, MPLAB, Arduino IDE.
• Assembler: Converts mnemonics→machine code (e.g., ASM51).
• Cross-Compiler: C/C++→hex (Keil C51, GCC).
• Linker/Locator: Combines objects, assigns addresses.
• Simulator: Software simulation without hardware.
• Emulator/ICE: Hardware replacement for real-time debug.
• Debugger: Breakpoints, step, register view.
• Programmer/Flash loader: ISP, boot-loader, USB programmers.
• Logic Analyzer, Oscilloscope, Burner.

Results of Given Instructions

(i) MOV A,#35H; ANL A,0FH → A=35H & 0FH = 05H. Result A=05H, upper nibble masked.

(ii) MOV A,#04H; ORL A,03H → 04H | 03H = 07H. A=07H (00000100 OR 00000011=00000111).

(iii) MOV A,#54H; XRL A,A → Any value XOR itself = 00H. A=00H, zero flag implied but flags unchanged for logic? Actually XRL affects? In 8051 logic ops do not affect CY/OV, but parity updated.

(iv) CLR C; MOV A,#26H; RRC A → A=26H=00100110B, C=0. RRC = rotate right through carry: new C= A0 (=0), A = (C old) concatenated >>1 = 0 0010011 = 13H. So A=13H, CY=0. If C started 0, result 13H. (If second rotation after? No). If assuming CLR C then RRC: A = 13H, C=0.

Summary table:
(i) 05H, (ii) 07H, (iii) 00H, (iv) 13H, CY=0.

Addressing Modes in Microprocessor (8051/8085) with Examples

• Immediate: Data in instruction. MOV A,#25H, MVI A,30H
• Register: Operands in registers. MOV A,R0, ADD A,R1, MOV A,B
• Direct: 8-bit direct address. MOV A,30H (internal RAM/SFR), STA 2500H
• Register Indirect: Address in register pair. MOV A,@R0, LDAX B, MOVX A,@DPTR
• Indirect (via memory pointer): MOV A,@A+DPTR (indexed)
• Indexed: Base+index e.g., MOVC A,@A+DPTR, MOVC A,@A+PC
• Relative: PC+offset SJMP -10H, JC LOOP
• Absolute: 11/16-bit address LJMP 1000H, AJMP LOOP
• Bit: Bit addressable SETB P1.0, CLR 20H.3
• Implied: NOP, CPL A

Each mode defines how effective address/data is fetched.

Instruction Types in 8085

• Data Transfer: MOV, MVI, LXI, LDA, STA, LHLD, SHLD, LDAX, STAX, XCHG, PUSH, POP, IN, OUT. E.g., MOV A,B copy B→A, LXI H,2500H load pointer.
• Arithmetic: ADD, ADC, SUB, SBB, INR, DCR, INX, DCX, DAD, DAA. E.g., ADD B A←A+B.
• Logical: ANA, ORA, XRA, CMP, CMA, RAL, RAR, ANI. E.g., ANA B A←A & B.
• Branching: JMP, JC, JZ, CALL, RET, RST, PCHL. JNZ 2000H
• Machine Control: NOP, HLT, DI, EI, SIM, RIM.

Each type corresponds to operation performed on data/address/control flow.

Data Transfer & Arithmetic Instructions – 8051

Data Transfer:

• MOV A,#55H, MOV A,30H, MOV A,@R0, MOV DPTR,#1234H, MOVC A,@A+DPTR, MOVX A,@DPTR, PUSH ACC, POP B, XCH A,R0, XCHD A,@R0
  Groups: Immediate, direct, indirect, DPTR.

Arithmetic:

• ADD A,R0 A←A+R0 (flags CY,AC,OV,P)
• ADDC A,R1 with carry
• SUBB A,R2 A←A - R2 - CY
• INC A, DEC R0, INC DPTR
• MUL AB B:A←A×B (OV if >255), 4 cycles
• DIV AB A←A/B, B←remainder
• DA A decimal adjust after ADD
  Examples illustrate covering all categories.

Program to Find Largest Number in Array (8051 Assembly)

ORG 0000H
MOV R0,#30H   ; array start 30H
MOV R1,#08H   ; count 8 example (adjust)
MOV A,@R0
MOV B,A       ; B holds max
INC R0
DEC R1
LOOP: MOV A,@R0
      CJNE A,B,NEXT ; compare
NEXT: JNC SKIP ; if A >= B (carry 0) -> new max
      SJMP CONT
SKIP: MOV B,A   ; update max
CONT: INC R0
      DJNZ R1,LOOP
      MOV 40H,B ; store result at 40H
      SJMP $
END

Algorithm: Initialize max with first element, iterate, if element > max update max. CJNE + JNC handles unsigned compare. For signed, handle OV.

C:

char arr[8]={12,45,23,78,34,56,90,11};
char max=arr[0];
for(i=1;i<8;i++) if(arr[i]>max) max=arr[i];

Subroutine & Its Execution

Definition: Subroutine (procedure/function) is reusable code block called from main via CALL, returns via RET/RETI.

Execution in 8051:

1. LCALL/ACALL addr pushes PC (return address) onto stack (SP++, low then high), loads subroutine address into PC, jumps.
2. Subroutine executes; may use PUSH/POP to preserve registers.
3. RET pops PC (high/low) from stack, resumes after CALL. RETI also clears interrupt priority for ISRs.

Types: LCALL (16-bit), ACALL (11-bit page). Nesting limited by stack size. Benefits: modularity, code saving. Example:

LCALL DELAY
;...
DELAY: MOV R7,#255
LOOP: DJNZ R7,LOOP
       RET

Addressing Modes of 8051 Microcontroller

Definition

An addressing mode specifies how an 8051 instruction identifies the operand or obtains the data on which the instruction operates.

The 8051 supports several addressing modes that provide flexibility for handling constants, registers, memory locations, bits, lookup tables, and branch destinations.

1. Immediate Addressing Mode

In immediate addressing, the constant data is specified directly in the instruction. The # symbol is used before the immediate value.

Example:

MOV A, #55H

Operation: The value 55H is loaded directly into the accumulator A.

Key point: The # symbol indicates immediate data.

---

2. Register Addressing Mode

In register addressing, the operand is present in one of the registers R0 to R7 of the currently selected register bank.

Example:

MOV A, R3

Operation: The contents of R3 are copied into the accumulator A.

Key point: The register itself contains the operand, not its address.

---

3. Direct Addressing Mode

In direct addressing, the instruction contains the 8-bit address of the operand directly. It can be used to access internal RAM locations and Special Function Registers (SFRs).

Example 1:

MOV A, 30H

This copies the contents of internal RAM location 30H into A.

Example 2:

MOV A, P1

This accesses the Port 1 SFR directly.

---

4. Register Indirect Addressing Mode

In register indirect addressing, a register contains the address of the operand rather than the operand itself.

For internal RAM, R0 or R1 can be used as indirect address registers.

Example:

MOV A, @R0

If R0 = 40H, the instruction loads A with the data stored at RAM location 40H.

The @ symbol indicates indirect addressing.

Key point: The register holds the address of the data.

---

5. Indexed Addressing Mode

Indexed addressing is mainly used for accessing lookup tables stored in program memory.

The effective address is obtained by adding the contents of the accumulator to a base address held in DPTR or the Program Counter.

Example:

MOVC A, @A+DPTR

Operation:

$$\text{Effective Address} = \text{DPTR} + \text{A}$$

The byte stored at this code-memory address is then loaded into A.

Application: Lookup tables, code conversion tables, seven-segment codes, etc.

---

6. Relative Addressing Mode

Relative addressing is used for short conditional and unconditional branches. An 8-bit signed displacement is added to the address of the instruction following the branch instruction.

Examples:

SJMP LABEL
JZ LABEL
JNZ LABEL

The typical relative range is:

$$-128 \text{ bytes} \; \text{to} \; +127 \text{ bytes}$$

from the address of the instruction following the branch.

Key point: Relative addressing is useful for nearby branches and loops.

---

7. Absolute Addressing Mode

Absolute addressing is used by the AJMP and ACALL instructions.

These instructions contain an 11-bit address field. The destination is formed within the same 2 KB page of program memory.

Example:

AJMP LABEL

Key point: AJMP/ACALL can transfer control within the current 2 KB program-memory page.

---

8. Long Addressing Mode

Long addressing is used by LJMP and LCALL. These instructions contain a complete 16-bit destination address.

Example:

LJMP 2500H

A 16-bit address allows access to the complete 64 KB program-memory address space of the standard 8051 architecture.

Key point: Long addressing provides a much larger program-memory range than absolute addressing.

---

9. Bit Addressing Mode

Bit addressing allows an instruction to access one individual bit in the bit-addressable internal RAM area or in bit-addressable SFRs.

Examples:

SETB P1.0
CLR C
JB P3.2, LABEL

For example, SETB P1.0 sets bit 0 of Port 1 to 1.

Application: Bit control, flags, digital I/O operations, and decision making.

---

Summary Table

Addressing Mode	Main Purpose	Example
Immediate	Use constant data	MOV A, #55H
Register	Use R0–R7 directly	MOV A, R3
Direct	Access RAM/SFR directly	MOV A, 30H
Register Indirect	Access data through an address in a register	MOV A, @R0
Indexed	Access lookup tables in program memory	MOVC A, @A+DPTR
Relative	Short branch operations	SJMP LABEL
Absolute	Branch/call within a 2 KB page	AJMP LABEL
Long	Branch/call anywhere in 64 KB program memory	LJMP 2500H
Bit	Access individual bits	SETB P1.0

Conclusion

The 8051 addressing modes provide efficient ways to access immediate data, registers, RAM, SFRs, individual bits, lookup tables, and program-memory locations. The major modes are immediate, register, direct, register indirect, indexed, relative, absolute, long, and bit addressing. Understanding these modes is essential for writing efficient 8051 assembly programs.

Subroutine Instructions & Stack Operations

Instructions: LCALL addr16 (3B, pushes PC+3, jumps 64K), ACALL addr11 (2B, page within 2K), RET (pops PC), RETI (pops + clears interrupt). LCALL vs ACALL tradeoff size vs range.

Stack Operations: Stack located in internal RAM, SP=07H reset, grows up. PUSH direct → SP++, [SP]←src; POP direct → dst←[SP], SP--. Used for saving ACC/PSW/B before subroutine/ISR. Example preservation:

PUSH ACC
PUSH PSW
; subroutine
POP PSW
POP ACC
RET

Overflow if SP > 7FH collides SFR region, so initialise MOV SP,#60H. Nesting limited by RAM.

Branching Instructions in 8051

• Unconditional jumps: LJMP addr16 (long), AJMP addr11 (absolute page), SJMP rel (short relative).
• Conditional jumps: JC rel (if CY=1), JNC, JZ, JNZ, JB bit,rel, JNB, JBC (jump if bit set then clear), DJNZ direct/Reg,rel (decrement & jump not zero), CJNE A,direct,rel / A,#data,rel / Rn,#data,rel / @Ri,#data,rel (compare & jump if not equal).
• Calls/Returns: LCALL, ACALL, RET, RETI.
• Indirect: JMP @A+DPTR.

Examples:

CJNE A,#10H,NOT_EQ
DJNZ R2,LOOP
JB P1.0,SET
LJMP FAR

Addressing Modes of 8051 – Detail with Examples

1. Immediate: MOV A,#0FFH
2. Register: MOV A,R2, ADD A,R1
3. Direct: MOV A,30H (internal RAM/SFR direct)
4. Indirect: MOV A,@R0, MOV @R1,A, MOVX A,@DPTR
5. Indexed: MOVC A,@A+DPTR, MOVC A,@A+PC
6. Relative: SJMP REL, JZ REL, DJNZ R0,REL (-128..127)
7. Absolute: AJMP addr11, ACALL
8. Long: LJMP addr16, LCALL
9. Bit: SETB P1.0, CLR ACC.2, MOV C,20H.3
10. Implied: NOP, CPL A, RLC A

Each distinguishes data source/destination encoding.

Subroutine – see Q70

Definition, CALL pushes PC, RET pops, types LCALL/ACALL, stack use, example DELAY routine. RETI for interrupt return. Benefits: modular, recursive via stack.

CJNE & DJNZ Instructions

CJNE (Compare and Jump if Not Equal): Four variants:

• CJNE A,direct,rel
• CJNE A,#data,rel
• CJNE Rn,#data,rel
• CJNE @Ri,#data,rel
  Operation: CY=1 if first < second, else 0; if not equal, PC←PC+rel else next. Does not store result, only sets CY and jumps. Example:

CJNE A,#10H,NOTEQ ; if A ≠10H jump

Use for compare, sorting.

DJNZ (Decrement & Jump if Not Zero): Two variants: DJNZ direct,rel, DJNZ Rn,rel. Decrement operand, if ≠0 jump. Useful for loops:

MOV R2,#10
LOOP: DJNZ R2,LOOP ; iterate 10 times

Neither affects flags except CY for CJNE; DJNZ affects none except operand.

OPCODE, OPERAND, Instruction Set & Data Transfer Categories

• OPCODE (Operation Code): Specifies operation, e.g., MOV, ADD, encoded as binary. In MOV A,#55H, MOV opcode is 74H.
• OPERAND: Data/address on which opcode acts, e.g., A, #55H, R0.

Instruction Set: Entire collection of opcodes a CPU can execute (8051 has 111 instructions).

3 Categories of Data Transfer:

1. Immediate/Internal → Register: MOV A,#data, MOV R0,A
2. Memory ↔ Register: MOVX A,@DPTR, MOVC, MOV A,@R0
3. Stack/Exchange: PUSH, POP, XCH, XCHD
   (Also grouped as CPU↔RAM, CPU↔SFR/Port, CPU↔External.)

Register & Direct Addressing Mode – 8051

• Register Addressing: Operand in R0-R7, A, B. Encoding selects register via 3-bit field within opcode, e.g., INC R3, ADD A,R2, MOV A,R5 – fast, 1 byte.
• Direct Addressing: 8-bit direct address follows opcode, accesses internal RAM 00-7FH or SFR 80-FFH directly, e.g., MOV A,30H load from RAM location 30H, MOV 30H,A, MOV P1,80H. Note: Direct accesses SFR when 80-FFH range; via indirect @R0 that accesses upper RAM not SFR. 2 bytes. Direct can also address bit as second byte.

Data Transfer & Arithmetic Instructions – Examples (as Q148)

Data Transfer:

• MOV A,#25H (immediate→A)
• MOV 30H,A (A→direct)
• MOV A,@R0 (indirect)
• MOV DPTR,#1000H
• MOVC A,@A+DPTR (table)
• MOVX A,@DPTR (external)
• PUSH ACC, POP B

Arithmetic:

• ADD A,R0 (A+=R0, CYOV)
• ADDC A,#10H with carry
• SUBB A,R1
• INC DPTR
• MUL AB, DIV AB, DA A (decimal adjust).

Example program snippet adding two arrays etc.

Short Notes: Addressing Modes of 8051 – see Q73

Immediate, register, direct, indirect, indexed, relative, absolute/long, bit, implied with examples MOV A,#data, MOV A,R0, MOV A,30H, MOV A,@R0, MOVC A,@A+DPTR, SJMP, LJMP, SETB.