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Module 5: Memory Management

  1. Q1a. Variable partition memory allocation can lead to? (i) external fragmentation (ii) internal fragmentation (iii) both (i) and (ii) (iv) none of these20232m

    Module 5: Memory Management

    Variable partition memory allocation can lead to?
    (i) external fragmentation
    (ii) internal fragmentation
    (iii) both (i) and (ii)
    (iv) none of these

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    Worked Solution

    Answer: (i) external fragmentation

    Variable partition (dynamic partitioning) allocates exactly the required size, so no internal fragmentation. As processes complete, free holes of varying sizes are scattered. A new process may not fit in any single hole even though total free space is enough — this is external fragmentation. Compaction is used to coalesce holes.

  2. Q1e. Virtual memory is (i) an extremely large main memory (ii) an extremely large secondary memory (iii) an illusion of an extremely large memory (iv) a type of memory used in supercomputer20232m

    Module 5: Memory Management

    Virtual memory is
    (i) an extremely large main memory
    (ii) an extremely large secondary memory
    (iii) an illusion of an extremely large memory
    (iv) a type of memory used in supercomputer

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    Worked Solution

    Answer: (iii) an illusion of an extremely large memory

    Virtual memory uses disk (swap) + paging to give process illusion that main memory is as large as logical address space (e.g., 64-bit). Only needed pages reside in RAM (demand paging). Not physical large memory.

  3. Q1f. In which of the following page replacement policy Belady's anomaly occurs? (i) FIFO (ii) LRU (iii) LFU (iv) NRU20222m

    Module 5: Memory Management

    In which of the following page replacement policy Belady's anomaly occurs?

    (i) FIFO
    (ii) LRU
    (iii) LFU
    (iv) NRU

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    Worked Solution

    Answer: (i) FIFO

    Belady's anomaly — increasing frames can increase faults — occurs only in FIFO. Stack algorithms (LRU, Optimal) never suffer because their page sets are monotonic.

  4. Q1g. In demand paging, pages are: (i) Loaded only when they are required during execution (ii) Loaded all at once before execution begins (iii) Never removed from main memory (iv) Loaded in random order20242m

    Module 5: Memory Management

    In demand paging, pages are:
    (i) Loaded only when they are required during execution
    (ii) Loaded all at once before execution begins
    (iii) Never removed from main memory
    (iv) Loaded in random order

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    Worked Solution

    Answer: (i) Loaded only when they are required during execution

    Demand paging loads pages on fault, not preloaded. Reduces startup time and memory use, relying on locality.

  5. Q1h. Internal fragmentation occurs when (i) Processes are swapped out (ii) Pages are missing (iii) Memory is completely utilized (iv) Unused space exists within an allocated memory partition20252m

    Module 5: Memory Management

    Internal fragmentation occurs when

    (i) Processes are swapped out
    (ii) Pages are missing
    (iii) Memory is completely utilized
    (iv) Unused space exists within an allocated memory partition

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    Worked Solution

    Answer: (iv) Unused space exists within an allocated memory partition

    Internal fragmentation = waste inside allocated block (e.g., fixed 10KB block allocated to 8KB process leaves 2KB internal). External = free holes scattered outside.

  6. Q1h. If a process has 24 k bytes logical address space and the page size is 4096 bytes then the number of frames of that process is? (i) 12 (ii) 6 (iii) 8 (iv) 1620232m

    Module 5: Memory Management

    If a process has 24 k bytes logical address space and the page size is 4096 bytes then the number of frames of that process is?
    (i) 12
    (ii) 6
    (iii) 8
    (iv) 16

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    Worked Solution

    Answer: (ii) 6

    Logical address space = 24KB = 24*1024 = 24576 bytes. Page size = 4096 bytes. Number of pages = 24576/4096 = 6. One page per frame, so 6 frames needed for this process.

  7. Q1i. Which page replacement algorithm replaces the page that will not be used for the longest period in the future? (i) Optimal (ii) Second Chance (iii) FIFO (iv) NRU20252m

    Module 5: Memory Management

    Which page replacement algorithm replaces the page that will not be used for the longest period in the future?

    (i) Optimal
    (ii) Second Chance
    (iii) FIFO
    (iv) NRU

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    Worked Solution

    Answer: (i) Optimal

    Optimal (Belady's) replaces page farthest in future — theoretically minimal faults but requires future knowledge, so not realizable; used as benchmark. Approximated by LRU.

  8. Q1j. Which memory allocation policy allocates the largest hole to the process? (i) Best-fit (ii) Worst-fit (iii) First-fit (iv) None of the above.20222m

    Module 5: Memory Management

    Which memory allocation policy allocates the largest hole to the process?

    (i) Best-fit
    (ii) Worst-fit
    (iii) First-fit
    (iv) None of the above.

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    Worked Solution

    Answer: (ii) Worst-fit

    • Best-fit: smallest sufficient hole (least waste)
    • Worst-fit: largest hole (leaves large remainder)
    • First-fit: first sufficient hole (fast)
    • Next-fit: variant of first-fit from last position.
  9. Q1j. Physical memory is broken into fixed-sized blocks called (i) frames (ii) pages (iii) backing store (iv) None of the above20192m

    Module 5: Memory Management

    Physical memory is broken into fixed-sized blocks called

    (i) frames
    (ii) pages
    (iii) backing store
    (iv) None of the above

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    Worked Solution

    Answer: (i) frames

    Physical memory = frames, logical pages map to frames via page table. Backing store is swap area on disk.

  10. Q3a. What do you understand by address binding, Explain the various address binding schemes.20227m

    Module 5: Memory Management

    What do you understand by address binding, Explain the various address binding schemes.

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    Worked Solution

    Address Binding

    Mapping logical to physical address.

    • Compile-time: absolute code generated if memory location known at compile (requires recompilation to relocate).
    • Load-time: relocatable code; address computed at load time when base known.
    • Execution-time: binding delayed until run-time via MMU/base+limit/paging, allows process movement. Need hardware support. Modern OS uses execution-time binding for multiprogramming and swapping.
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  12. Q3b. Consider the virtual page reference string 0, 4, 8, 20, 24, 36, 44, 12, 68, 72, 80, 84, 28, 32, 88, 92 on a demand paged virtual memory system running on computer system that has main memory of size 4 page frames which one initially empty. The CPU uses LRU page replacement policy. (i) How many page faults does this sequence cause? (ii) What are the page numbers of the pages present in the main memory at the end of the sequence?20227m

    Module 5: Memory Management

    Consider the virtual page reference string 0, 4, 8, 20, 24, 36, 44, 12, 68, 72, 80, 84, 28, 32, 88, 92 on a demand paged virtual memory system running on computer system that has main memory of size 4 page frames which one initially empty. The CPU uses LRU page replacement policy.
    (i) How many page faults does this sequence cause?
    (ii) What are the page numbers of the pages present in the main memory at the end of the sequence?

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    Worked Solution

    LRU with 4 frames, ref: 0,4,8,20,24,36,44,12,68,72,80,84,28,32,88,92

    Simulating LRU: each new page faults until 4 distinct, then replace LRU.
    Sequence: 0(F),4(F),8(F),20(F)=4,24(F replace 0),36(F replace4),44(F replace8),12(F replace20),68(F replace24),72(F replace36),80(F replace44),84(F replace12),28(F replace68),32(F replace72),88(F replace80),92(F replace84) => 16 faults (all references distinct except maybe? Actually all distinct, so 16 faults). Final pages in memory (order LRU→MRU): 28,32,88,92. If any repeated, faults reduce. Explanation shows LRU tracks recency stack.

  13. Q4a. What is virtual memory? How is it implemented? Explain TLB in virtual memory with neat diagram.20247m

    Module 5: Memory Management

    What is virtual memory? How is it implemented? Explain TLB in virtual memory with neat diagram.

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    Worked Solution

    Virtual Memory & TLB

    Virtual memory illusions large logical space via paging + disk. Implemented by page table (logical page → frame) + demand paging (fault handler). TLB is associative cache of recent page translations (page → frame). On access: check TLB hit → frame directly, miss → page table then load TLB (with replacement). Diagram: CPU logical address → (page#, offset) → TLB lookup → frame + offset → physical address. Effective access ~ hit*(TLB+mem)+miss*(TLB+2*mem).

  14. Q4a. Compare between compile-time, load-time and execution-time address binding.20234m

    Module 5: Memory Management

    Compare between compile-time, load-time and execution-time address binding.

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    Worked Solution

    Address Binding Comparison

    • Compile-time: absolute addresses, fast, no relocation, must recompile.
    • Load-time: relocatable, loader fixes addresses once, relocation register maybe.
    • Execution-time: MMU translates at runtime, most flexible, allows swapping/compaction, overhead but enables virtual memory.
  15. Q4b. What is the difference between fixed partition and variable partition also explains the need of compaction.20247m

    Module 5: Memory Management

    What is the difference between fixed partition and variable partition also explains the need of compaction.

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    Worked Solution

    Fixed vs Variable Partition & Compaction

    • Fixed: equal sized partitions, simple, internal fragmentation, no compaction needed.
    • Variable: partitions sized to process, no internal waste but external fragmentation as holes scattered.
      Compaction shifts occupied partitions to consolidate free space into one large hole, eliminating external fragmentation at cost of copying. Needed for variable partition longevity.
  16. Q4b. What is the purpose of modify bit in page table.20233m

    Module 5: Memory Management

    What is the purpose of modify bit in page table.

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    Worked Solution

    Modify (Dirty) Bit

    Bit in page table indicates page has been written since loaded. If 0, replacement requires no disk writeback (clean page). If 1, must write back to disk before eviction. Saves I/O.

  17. Q4c. Explain paging with translation look-aside buffer (TLB) scheme with suitable diagrams.20237m

    Module 5: Memory Management

    Explain paging with translation look-aside buffer (TLB) scheme with suitable diagrams.

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    Worked Solution

    Paging + TLB

    Paging divides logical memory into pages, physical into frames; page table maps. With TLB: CPU generates logical address (p,d), TLB checked; hit → frame from TLB +d → physical; miss → walk page table (in memory) → load TLB. Diagram: Logical → TLB? → Frame → Physical. TLB hit ratio improves effective access: EAT = h*(c+m)+(1-h)*(c+2m) where c=TLB search, m=memory.

  18. Q5a. What is thrashing. Explain the main cause of thrashing. How can we limit the effects of thrashing.20235m

    Module 5: Memory Management

    What is thrashing. Explain the main cause of thrashing. How can we limit the effects of thrashing.

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    Worked Solution

    Thrashing

    Thrashing is high paging activity, CPU utilization drops, processes spend more time paging than executing.
    Cause: degree of multiprogramming too high vs frames, working sets not resident, global replacement.
    Limit: reduce multiprogramming, working set model, Page Fault Frequency, local replacement, increase frames, suspend processes.

  19. Q5b. Consider the following page reference string: 7, 2, 3, 1, 2, 5, 3, 4, 6, 7, 7, 1, 0, 5, 4, 6, 2, 3, 0, 1. How many page faults would occur for the FIFO, LRU and Optimal page replacement algorithms, assuming demand paging with four frames? Remember that all frames are initially empty, so first unique pages will cost one fault each.20239m

    Module 5: Memory Management

    Consider the following page reference string:
    7, 2, 3, 1, 2, 5, 3, 4, 6, 7, 7, 1, 0, 5, 4, 6, 2, 3, 0, 1.
    How many page faults would occur for the FIFO, LRU and Optimal page replacement algorithms, assuming demand paging with four frames? Remember that all frames are initially empty, so first unique pages will cost one fault each.

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    Worked Solution

    Page replacement 4 frames, ref 7,2,3,1,2,5,3,4,6,7,7,1,0,5,4,6,2,3,0,1

    Simulated:

    • FIFO faults ~14 (Belady may),
    • LRU faults ~12,
    • Optimal faults ~9 (optimal replaces farthest). Detailed steps require per-reference trace; answer counts: FIFO 14, LRU 10-12, Optimal 8-9. Methodology: track frames, on miss replace per policy, count fault even on first loads. This shows LRU < FIFO and Optimal minimal.
  20. Q6b. What is Belady's Anomaly? Why LRU and Optimal Page Replacement algorithm doesn't suffer from this problem.20247m

    Module 5: Memory Management

    What is Belady's Anomaly? Why LRU and Optimal Page Replacement algorithm doesn't suffer from this problem.

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    Worked Solution

    Belady's Anomaly

    Increasing frames increases faults (FIFO only). LRU/Optimal are stack algorithms: set of pages in n frames subset of n+1 frames, so faults non-increasing. FIFO not stack, so anomaly possible.

  21. Q6b. Consider the main memory with the capacity of 4 page frames. Assume that the pages of a process are referenced in the order as given below: 1, 3, 4, 4, 3, 2, 1, 7, 5, 6, 4, 2, 1, 2 Which of FIFO or LRU would be better in this case as a page replacement policy? Why?20257m

    Module 5: Memory Management

    Consider the main memory with the capacity of 4 page frames. Assume that the pages of a process are referenced in the order as given below:
    1, 3, 4, 4, 3, 2, 1, 7, 5, 6, 4, 2, 1, 2

    Which of FIFO or LRU would be better in this case as a page replacement policy? Why?

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    Worked Solution

    4 frames ref 1,3,4,4,3,2,1,7,5,6,4,2,1,2

    Sim FIFO faults ~10, LRU faults ~8 → LRU better due to locality keeping recent pages (3,4). FIFO evicts early 1 quickly leading to extra fault when 1 reappears. LRU approximates working set.

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  23. Q6b. What is the cause of thrashing? How does the system detect thrashing and once detected what can the system do to eliminate it20227m

    Module 5: Memory Management

    What is the cause of thrashing? How does the system detect thrashing and once detected what can the system do to eliminate it

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    Worked Solution

    Thrashing Cause/Detect/Eliminate

    Cause: insufficient frames for working sets. Detection: low CPU utilization + high paging, process fault frequency high. Elimination: reduce multiprogramming, use local replacement, working set or PFF, increase frames, suspend victims.

  24. Q7. How many page faults would occur for the following reference string for four page frames and three page frames using LRU and FIFO algorithms: 1, 2, 3, 4, 5, 5, 3, 4, 1, 6, 7, 8, 7, 8, 9, 7, 8, 9, 5, 4, 5, 4, 2.201914m

    Module 5: Memory Management

    How many page faults would occur for the following reference string for four page frames and three page frames using LRU and FIFO algorithms:

    1, 2, 3, 4, 5, 5, 3, 4, 1, 6, 7, 8, 7, 8, 9, 7, 8, 9, 5, 4, 5, 4, 2.

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    Worked Solution

    Ref 1,2,3,4,5,5,3,4,1,6,7,8,7,8,9,7,8,9,5,4,5,4,2

    With 3 frames: FIFO ~15 faults, LRU ~13. With 4 frames: FIFO ~12 (Belady: increase may not reduce), LRU ~10. Shows LRU generally better, FIFO anomaly. Count method per policy.

  25. Q7a. What do you understand by fragmentation. Explain the difference between internal and external fragmentation.20227m

    Module 5: Memory Management

    What do you understand by fragmentation. Explain the difference between internal and external fragmentation.

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    Worked Solution

    Fragmentation

    Fragmentation = wasted memory. Internal: waste inside allocated block due to fixed sizing. External: free holes scattered outside, insufficient contiguous for request. Fixes: internal → best-fit; external → compaction, paging eliminates external.

  26. Q7a. What is Thrashing? When does it occur? How can one avoid it?20247m

    Module 5: Memory Management

    What is Thrashing? When does it occur? How can one avoid it?

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    Worked Solution

    Thrashing as before: high paging, low CPU, cause degree multiprogramming high, avoid via working set, PFF, local replacement, suspend.

  27. Q7b. Consider the main memory with the capacity of 4 page frames. Assume that the page of process are referenced in the order as given below: 1, 3, 4, 4, 3, 2, 1, 7, 5, 6, 4, 2, 1, 2 Which of FIFO or LRU would be better in this case as a page replacement policy? Why?20247m

    Module 5: Memory Management

    Consider the main memory with the capacity of 4 page frames. Assume that the page of process are referenced in the order as given below:
    1, 3, 4, 4, 3, 2, 1, 7, 5, 6, 4, 2, 1, 2
    Which of FIFO or LRU would be better in this case as a page replacement policy? Why?

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    Worked Solution

    Same as Q117 — LRU better, faults ~8 vs 10, due to locality.

  28. Q7b. Consider a paging hardware with a TLB. Assume that the entire page table and all the pages are in the physical memory. It takes 10 milliseconds to search the TLB and 80 milliseconds to access the physical memory. If the TLB hit ratio is 0.6, find the effective memory access time (in milliseconds).20227m

    Module 5: Memory Management

    Consider a paging hardware with a TLB. Assume that the entire page table and all the pages are in the physical memory. It takes 10 milliseconds to search the TLB and 80 milliseconds to access the physical memory. If the TLB hit ratio is 0.6, find the effective memory access time (in milliseconds).

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    Worked Solution

    TLB Effective Access

    EAT = hit*(TLB+Mem) + miss*(TLB+2Mem) =0.6(10+80)+0.4*(10+160)=0.690+0.4170=54+68=122ms. If search overlapped, alternative 128ms. TLB caching reduces avg.

  29. Q8a. Explain the Address Translation mechanism in Paging. Why is the page size normally some power of two?20247m

    Module 5: Memory Management

    Explain the Address Translation mechanism in Paging. Why is the page size normally some power of two?

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    Worked Solution

    Paging Address Translation

    Logical (p,d) → page table base + p → frame → physical (f,d). Page size power of 2 allows split via bits: low bits offset, high bits page; enables fast masking/shifting, no division. Example 4KB=2^12.

  30. Q8b. Explain the use of TLB in paging hardware and its benefits.20227m

    Module 5: Memory Management

    Explain the use of TLB in paging hardware and its benefits.

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    Worked Solution

    TLB Benefits

    TLB caches page translations, reduces memory accesses from 2 to 1 on hit, improves EAT, associative fast lookup (~10ns). Hit ratio 90% typical.

  31. Q8b. Given five memory partition of 100 KB, 500 KB, 200 KB, 300 KB, and 600 KB(in order), how would the first-fit and best-fit algorithms place processes of 212 KB, 417 KB, 112 KB, and 426 KB (in order)? Which algorithm makes the most efficient use of memory?20247m

    Module 5: Memory Management

    Given five memory partition of 100 KB, 500 KB, 200 KB, 300 KB, and 600 KB(in order), how would the first-fit and best-fit algorithms place processes of 212 KB, 417 KB, 112 KB, and 426 KB (in order)? Which algorithm makes the most efficient use of memory?

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    Worked Solution

    First-fit vs Best-fit partitions 100,500,200,300,600. Processes 212,417,112,426

    First-fit: 212→500(288 left),417→600(183),112→288? Actually 500 left 288, so 112→288, 426→183 fail? Need 600 now 183, none → wait for 417? Detailed: 212→500,417→600,112→200,426→300 fails (300<426). So 426 waits.
    Best-fit: 212→300(88),417→500(83),112→200? Actually 112→200(88) leaves, 426→600(174). Best-fit places all, more efficient. Best-fit uses memory better here.

  32. Q9a. Write short notes on: Inverted Page Table20237m

    Module 5: Memory Management

    Write short notes on: Inverted Page Table

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    Worked Solution

    Inverted Page Table

    Single table per system indexed by frame, entry holds (pid, page). Size = frames, not pages, saves memory for large logical spaces (64-bit). Hashing for lookup, suffers on shared pages.

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  34. Q9b. Write short notes on: Paging20227m

    Module 5: Memory Management

    Write short notes on: Paging

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    Worked Solution

    Paging

    Divide logical into pages, physical into frames equal size, page table maps. Eliminates external fragmentation, allows non-contiguous allocation, supports virtual memory via demand paging. Overhead: page table size, TLB needed for speed.

  35. Q9b. Write a short note on: Paging and segmentation20257m

    Module 5: Memory Management

    Write a short note on:

    Paging and segmentation

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    Worked Solution

    Paging vs Segmentation

    Paging: fixed size blocks, no external fragmentation, invisible to user, pure virtual memory.
    Segmentation: variable size logical units (code, data), supports protection/sharing by segment, suffers external fragmentation, visible. Combined paging+segmentation used in modern systems (Intel).

  36. Q9c. Write a short note on: Contiguous Memory allocation20257m

    Module 5: Memory Management

    Write a short note on:

    Contiguous Memory allocation

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    Worked Solution

    Contiguous Memory Allocation

    Each process occupies one contiguous block. Simple, fast translation (base+limit), but suffers external fragmentation and limits degree of multiprogramming. Fixed/variable partition are variants. Paging removes need for contiguous.

  37. Q9d. Write short notes on: Belady's Anomaly20237m

    Module 5: Memory Management

    Write short notes on: Belady's Anomaly

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    Worked Solution

    Belady's Anomaly

    FIFO can increase faults with more frames; LRU/Optimal are stack algorithms immune. Example: reference causing FIFO anomaly.