Target Code Generation
1. Task
Target code generation maps optimized IR to real machine instructions: select ops, order them, allocate registers, emit assembly/object. Must be correct, then fast/compact.
2. Steps
1. instruction selection (tile IR: a+b → ADD; a*2 → SHL)
2. register allocation (see prev topic)
3. instruction ordering/scheduling (pipeline)
4. emit + fixups (labels, relocations, ABI calls)
Tiling example x=a+b*c:
t1=b*c → MUL R1,b,c | t2=a+t1 → ADD R2,a,R1 | x=t2 → ST x,R2
3. Issues
- CISC vs RISC: complex tiles vs load-store + many regs.
- ABI: call conventions, callee/caller-saved regs, stack alignment.
- Peephole cleans artifacts after emit.
4. Quality Measures
Correctness > speed (cycles) + size (embedded) + power. Verified by testing + formal tilers (BURS).
5. Exam Points
- List codegen steps with example — 7 marks, very frequent.
- Instruction selection (tiling) example — 5 marks, frequent.
- ABI / callee-saved role — 3 marks, frequent.