Five Important Instruction Set Design Issues

1. Operation Repertoire (Operations to Provide)

What operations - data movement (LOAD/STORE), arithmetic (ADD,SUB,MUL,DIV), logical (AND/OR/SHIFT), control (BRANCH,CALL), I/O. Need completeness (all uses) vs orthogonality. Too many ops -> complex decode; too few -> inefficient programs (e.g., no multiply must emulate). RISC keeps ~50-100 simple ops; CISC has >200 complex.

2. Data Types & Operand Representations

What types supported natively - integer (8/16/32/64b), floating (IEEE754), decimal/BCD, char/string, boolean. Affects ALU design and format. Choice of word length, endianness, signed (2's complement) vs unsigned.

3. Instruction Format & Length

Fixed vs variable length, number of fields: opcode + operands + addressing mode + immediate. Tradeoff: fixed (RISC, e.g., 32b, 3-reg) simple fetch/decode but code density low; variable (x86, 1-15B) dense but complex decoder. Number of addresses per instruction: 0 (stack),1 (accumulator),2,3-address.

4. Addressing Modes

How operand address specified:

• Immediate, Direct, Register, Register-Indirect, Indexed ($EA=Base+Index\times scale$), Autoincrement, PC-relative, Stack.
  More modes -> flexibility but hardware complexity & CPI variance. Must balance for compilers (RISC favors Reg+Immediate+Displacement only).

5. Registers - Number, Use, Organization

How many visible registers? 8 (x86), 32 (MIPS/ARM). General Purpose vs specialized (accumulator, index). Affects operand fetching, procedure call convention, spill to memory, context switch cost. Also interacts with instruction format (3-bit vs 5-bit reg fields).

Bonus (mention any):

• Instruction Set Orthogonality & Completeness - all modes work with all ops vs irregular.
• Control Flow & Condition Codes - how branches/flags handled.
• Memory Alignment & Byte Ordering

Good design balances code density, CPI, decode simplicity, compiler target, backward compatibility.