Answer: (ii) Data hazard

Explanation

A data hazard occurs when an instruction needs a value that a previous, still-in-flight instruction has not yet written back. The most common form is RAW (read-after-write):

ADD R1, R2, R3     ; writes R1
SUB R4, R1, R5     ; reads R1 -> must wait for the ADD result

Remedies: pipeline stalls, forwarding (bypassing), and compiler instruction scheduling (placing independent instructions in between).

• Structural hazard: two instructions need the same hardware resource at the same time.
• Control hazard: caused by branches.
• "Syntax hazard" and "memory hazard" are not standard pipeline hazard classes.

$$\boxed{\text{(ii) Data hazard}}$$