MICROPROCESSORS

Answer: (ii) Internal interrupts

Explanation: Port 3 (P3.0–P3.7, pins 10–17) in 8051 has alternate functions:

• P3.0 = RxD (serial input), P3.1 = TxD (serial output) → serial ports
• P3.2 = INT0, P3.3 = INT1\ → external interrupts
• P3.4 = T0, P3.5 = T1 (timer inputs)
• P3.6 = WR, P3.7 = RD\ → external memory read/write strobes

There is no alternate function for "internal interrupts" on Port 3. All other options are valid Port-3 alternate functions. Hence (ii) does not belong.

Answer: (ii) 16-bit

Explanation: The Program Counter (PC) in 8051 is a 16-bit register. It holds the address of the next instruction to be fetched. Because 8051 can address up to 64K bytes of program memory (0000H–FFFFH), PC must be 16 bits wide. It is automatically incremented after each fetch and is affected by jumps, calls, and branches.

Answer: (ii) \overline{PSEN}

Explanation: \overline{PSEN} (Program Store Enable) is the 8051 control output that:

• Pulses low once every 6 oscillator periods (once per machine cycle) when fetching code from external program memory.
• Stays high (inactive, because it is active-low) almost continuously when execution is from internal program memory, going low only if an external access is needed.
• ALE also pulses every 6 osc periods but is not specific to external code fetch and pulses even during internal execution (except when disabled). \overline{EA} is an input, not an output. Hence the description matches \overline{PSEN}.

Answer: (iv) All of the above

Explanation: Crystal oscillators (quartz) are preferred over ceramic resonators for 8051 because:

1. Ceramic resonators are available with lower frequency accuracy and do not reliably offer 12 MHz and higher frequencies with required stability.
2. Resonators are less stable over temperature and aging compared to quartz crystals, causing baud-rate and timing errors.
3. The cost saving of a resonator vs crystal is negligible compared to overall MCU board cost, so there is no compelling cost advantage.
   Hence all statements are true, resonators are not preferred.

Answer: (iii) 16 bytes

Explanation: In 8051 internal RAM (00H–7FH), the region 20H–2FH (16 bytes × 8 bits = 128 bits) is bit-addressable. Bits are addressed as 00H–7FH in bit address space. Additionally, most SFRs with addresses ending in 0H or 8H are bit-addressable, but the question asks about RAM area, which is 16 bytes. Some textbooks note 16 bytes = 128 bits.

Answer: (i) Intel

Explanation: The 8051 microcontroller family was developed by Intel in 1980 (MCS-51). Intel's original 8051 had 4K ROM, 128 bytes RAM, 32 I/O lines, two 16-bit timers, and serial port. Later variants by Atmel, Philips/NXP, etc., are second-sourced. AMD, IBM, Motorola did not develop 8051.

Answer: (i) IE

Explanation: IE = Interrupt Enable register (address A8H) in 8051. Bit EA (IE.7) is the global enable; bits ES, ET1, EX1, ET0, EX0 individually enable/disable serial, Timer1, External1, Timer0, External0 interrupts. IP = Interrupt Priority, TCON controls interrupt flags and timer run, PCON is power control. So IE enables/disables interrupts.

Answer: (ii) Top of stack

Explanation: Stack Pointer (SP) is an 8-bit register (address 81H) that holds the address of the top of stack - the last pushed byte in internal RAM. On PUSH, SP increments then stores; on POP, data retrieved then SP decrements. After reset SP=07H, so stack grows from 08H upwards.

Answer: (iv) Port 3 (also Port 0 and Port 2 have dual function, but most dual is Port 3)

Explanation: All ports except Port 1 have dual functions:

• Port 0: I/O + AD0-AD7 multiplexed address/data + external memory
• Port 2: I/O + A8-A15 high address
• Port 3: I/O + alternate functions (RxD, TxD, INT0/1, T0/T1, WR, RD)
  Port 1 is quasi-bidirectional I/O only. Among options, Port 3 is the classic "dual functionality" with 8 alternate functions, and in a single-choice question the expected answer is Port 3 (if multiple, Port 0 & 2 also have dual, but Port 3 is the most prominent). If forced to one: Port 3.

Answer: (iv) 07H

Explanation: After reset, SP = 07H in 8051. Therefore the first PUSH increments SP to 08H (first stack location, which is also the start of the user RAM above register banks 0-3). Many textbooks initialise SP to 60H to avoid overlap, but default reset value is 07H.

Answer: (ii) OV

Explanation: OV (Overflow) flag in PSW (PSW.2) indicates signed overflow (carry into sign bit XOR carry out). To correctly detect signed addition/subtraction results, OV is examined along with CY for unsigned. CY alone handles unsigned carry/borrow. AC is auxiliary carry for BCD, FO is user flag (PSW.5). So OV allows both signed and unsigned operations to be distinguished (e.g., ADD vs ADDC with overflow check).**

Answer: (iii) 16 bytes of internal RAM from 20H to 2FH

Explanation: Bit-addressable RAM in 8051 is exactly 16 bytes at 20H–2FH (128 bit addresses 00H–7FH). Certain SFRs (80H, 88H, 90H ... F0H) are also bit-addressable, but the RAM bit-addressable area is 20H–2FH. Entire RAM (00H–FFH) is not bit-addressable.

Answer: (ii) Voltage transitions with respect to time

Explanation: A timing diagram plots logic levels (high/low) vs time, showing propagation delays, setup/hold times, bus cycles, clock phases, and signal transitions (e.g., ALE, PSEN, RD/WR). It does not show program logic or machine code directly.

Answer: (i) Push

Explanation: In 8051, stack grows upward. PUSH increments SP first, then stores byte: SP←SP+1; [SP]←src. POP decrements after read: dst←[SP]; SP←SP-1. So incremental phase corresponds to PUSH. RET/POP decrement SP.

Answer: (i) Accumulator

Explanation: Accumulator (ACC, A register, address E0H) is the primary working register for ALU in 8051 and 8085. Most arithmetic-logic operations take one operand from A and store result back into A. SFR, Timer, SP do not hold ALU results.

Answer: (ii) 4

Explanation: 8051 has 4 parallel 8-bit I/O ports: Port 0 (P0), Port 1 (P1), Port 2 (P2), Port 3 (P3) → 32 I/O lines total. Each can be used as input/output, with alternate functions on P0, P2, P3.

Answer: (iii) 40

Explanation: Standard 8051 (DIP-40) has 40 pins: 32 I/O (P0-P3), 2 crystal (XTAL1/2), RST, EA/VPP, ALE/PROG, PSEN, VCC, VSS. Other packages (PLCC-44, TQFP-44 with 44 pins) exist, but classic 8051 is 40-pin DIP.

Answer: (i) Latches lower address byte

Explanation: ALE = Address Latch Enable. In multiplexed mode (Port 0 = AD0-AD7), ALE pulses high to enable external latch (74LS373) to capture low-order address byte (A0-A7) at beginning of machine cycle; data then appears on same port. It does not enable timers, select internal memory, or control interrupts.

Answer: (i) HMOS

Explanation: HMOS version of MCS-51 (e.g., 8051 original) requires an external clock source to be connected to XTAL2 with XTAL1 grounded when driven externally. CHMOS/CMOS versions (80C51) use XTAL1 as clock input and leave XTAL2 floating. Hence HMOS is the version described.

Answer: (i) Address Latch Enable

Explanation: ALE stands for Address Latch Enable - the 8051 output that controls external latch for demultiplexing low address from Port 0.

Answer: (iv) 5

Explanation: 8051 has 5 interrupt sources (interrupt vector addresses):

1. INT0 (0003H) external
2. Timer 0 overflow TF0 (000BH)
3. INT1 (0013H) external
4. Timer 1 overflow TF1 (001BH)
5. Serial RI+TI (0023H)
   Some derivatives add extra, but classic 8051 has 5; 2 are external hardware interrupts.

Answer: (ii) Level triggering

Explanation: External interrupts INT0/INT1 can be edge-triggered (IT0/IT1=1, falling edge) or level-triggered (IT0/IT1=0, low level). Level-triggered requires the signal to stay low until the interrupt is serviced and the external source releases it; otherwise repeated interrupts or missed flag clearing occur. Edge-triggered needs only a falling edge.

Special Function Registers (SFRs) in 8051

SFRs occupy internal RAM 80H–FFH (only addresses ending 0H/8H bit-addressable, total 21-26 SFRs). Key SFRs:

SFR	Address	Purpose
ACC (A)	E0H	Accumulator, ALU results
B	F0H	Multiply/divide, storage
PSW	D0H	Flags: CY, AC, FO, RS1,RS0, OV, P
SP	81H	Stack Pointer
DPL/DPH	82H/83H	Data Pointer 16-bit for external access
P0-P3	80H,90H,A0H,B0H	I/O ports
IE	A8H	Interrupt Enable (EA, ES, ET1,EX1,ET0,EX0)
IP	B8H	Interrupt Priority
TCON	88H	Timer control (TF1,TR1,TF0,TR0,IE1,IT1,IE0,IT0)
TMOD	89H	Timer mode (GATE,C/T,M1,M0)
TH0/TL0, TH1/TL1	8AH-8DH	Timer counts
SCON	98H	Serial control (SM0,SM1,SM2,REN,TB8,RB8,TI,RI)
SBUF	99H	Serial buffer (TX/RX)
PCON	87H	Power control (SMOD, IDL, PD)

Bit-addressable SFRs (marked *) allow SETB/CLR. Maps allow direct bit manipulation for control. Example: SETB TR1 starts Timer1; JNB TF0 loop etc.

Interrupt Controller in 8051 – Functions & Programming

Sources (5): INT0 (0003H), Timer0 (000BH), INT1 (0013H), Timer1 (001BH), Serial (0023H). Priority via IP register, enable via IE.

Registers:

• IE (A8H): EA (global) | - | - | ES | ET1 | EX1 | ET0 | EX0 ; set to enable.
• IP (B8H): PS | PT1 | PX1 | PT0 | PX0 – 1=high priority.
• TCON (88H): IT1,IT0 (edge/level), IE1/IE0 (flags), TF1/TF0, TR1/TR0.

Programming:

MOV IE,#10000101B ; EA=1, ES=0, ET1=1, EX1=0, ET0=1, EX0=1 -> enable INT0, T0, T1
MOV IP,#00000001B ; PX0 high priority
SETB IT0 ; edge triggered INT0

Working: When interrupt occurs, flag set, if enabled & priority allows, CPU finishes current instruction, pushes PC, vectors to ISR address, clears flag (TI/RI not auto-cleared), RETI pops PC and restores. Nested interrupts allowed via high priority.

Example ISR stub: ORG 0003H ; LJMP EXT0_ISR.

I/O Port Pins Functions in 8051

8051 has 4×8-bit ports (32 lines), each bidirectional with internal pull-ups except P0 open-drain for external memory.

• Port 0 (P0.0-P0.7, pins 32-39): Quasi I/O when internal memory used; Alternate: AD0-AD7 multiplexed address/data bus for external program/data memory. Needs external pull-ups when used as I/O.
• Port 1 (P1.0-P1.7, pins 1-8): Dedicated I/O only (quasi-bidirectional, pull-ups), no alternate. Often for LED, keypad, etc. Some derivatives add alternate (T2, etc.).
• Port 2 (P2.0-P2.7, pins 21-28): I/O plus A8-A15 high address byte for external memory (when P0 low byte latched). Maintains high address during data phase.
• Port 3 (P3.0-P3.7, pins 10-17): I/O plus 8 alternates: P3.0 RxD (serial in), P3.1 TxD (serial out), P3.2 INT0, P3.3 INT1, P3.4 T0, P3.5 T1, P3.6 WR, P3.7 RD. Alternate enabled via SFR bits (SCON, TCON, IE).

Each port SFR (80H,90H,A0H,B0H) latch; reading drives pin state. Writing 1 makes pin input (floating with pull-up) for reading external.

8051 Internal Block Diagram – Description

Major blocks:

• CPU: 8-bit ALU + Accumulator + B + PSW flags + Temp registers.
• Program Memory (4KB ROM) + Data Memory (128B RAM) Harvard, separate buses. RAM: 00-1FH 4 banks, 20-2FH bit-addressable, 30-7FH general, 80-FFH SFRs.
• Instruction Register & Decoder, Timing & Control, Oscillator (XTAL1/2): 12-clock machine cycle, generates ALE, \overline{PSEN}, RD, WR.
• Interrupt Controller: 5 sources as before → priority encoder.
• Timer/Counter 0 &1: 16-bit, TMOD/TCON/TH/TL.
• Serial Port: UART with SCON/SBUF, baud via Timer1.
• I/O Ports P0-P3: latches + drivers + pin logic.
• Special Function Registers, DPTR (16-bit), PC (16), SP (8), buses: internal 8-bit data, 16-bit address via P0/P2.

Data flow: Oscillator drives control → fetches via PC→ROM→IR→decode → ALU/SFR/port/timer ops → ports/timers/serial run in parallel. Program and data fetch can overlap via separate buses. Textual diagram sufficient; enumerate connections: ALE→latch, PSEN→ROM, RD/WR→RAM/peripherals.

Sketch: Center CPU, top program ROM via bus, bottom RAM+SFRs, left ports, right oscillator+interrupt+timer+serial.

Role of Program Counter (PC) and Timing Circuits in 8051

PC (16-bit): Holds address of next instruction byte to fetch. After reset 0000H. Auto-increments per fetch, loaded by jumps/calls/interrupts/RET. Enables sequential execution and branching; width allows 64K program space.

Timing Circuits: Internal oscillator (XTAL1/2 + crystal, 2 inverters) generates clock, divided by 12 to produce machine cycle (6 states S1-S6 ×2 phases). Generates ALE (latching), \overline{PSEN} (fetch), RD/WR, and TIMER clock (Fosc/12). Provides state timing (T-states) for fetch-decode-execute, baud generation, timer increments. Also handles reset timing, power-on delay, and idle/power-down modes via PCON. Without precise timing, instruction sequencing, bus multiplexing, and serial communication fail.

16-bit Registers in 8051

8051 has two main 16-bit registers: DPTR (Data Pointer) and PC (Program Counter). SP is 8-bit but points to 8-bit addresses. Some count also Timer0/1 (THx:TLx) as 16-bit counters.

1. DPTR (DPL 82H + DPH 83H): 16-bit pointer for external data/code access (MOVX A,@DPTR, MOVC A,@A+DPTR). Can be incremented (INC DPTR) and used as two 8-bit registers.
2. PC (16-bit): Holds next fetch address, invisible to direct move but affected by LJMP, etc.
3. Timer0 & Timer1: Each 16-bit (TH0:TL0, TH1:TL1) for timing/counting, baud generation.
   If counting broadly, 4×16-bit including timers.

Functions: Addressing 64K external memory, sequencing code, timing, stack is 8-bit but extended via DPTR manipulation.

Oscillator Circuit & Timing in 8051

Oscillator: Crystal between XTAL1 (19) and XTAL2 (18) with 33pF caps to GND, plus internal inverter amplifier. Typically 11.0592 MHz (baud friendly) or 12 MHz (1µs cycle). Generates clock divided by 12 → machine cycle. Can also inject external clock to XTAL1 with XTAL2 floating (CMOS) or XTAL2 for HMOS.

Timing: One machine cycle = 12 oscillator periods = 6 states S1-S6 ×2 phases P1/P2. Most instructions 1-4 machine cycles: e.g., MOV A,Rn 1 cycle (1.085µs @11.0592M), MUL AB 4 cycles. ALE pulses at 1/6 Fosc, \overline{PSEN} active low during external fetch. Timer increments each machine cycle. Baud = (2^SMOD/32)*(Fosc/12/(256-TH1)). Reset requires 2 machine cycles high on RST.

SFRs Used in 8051 (Detailed as Q117)

List with addresses and function:
ACC E0H, B F0H, PSW D0H (CY,AC,F0,RS1,RS0,OV,P), SP 81H, DPL 82H, DPH 83H, P0 80H, P1 90H, P2 A0H, P3 B0H, IE A8H (EA, ES, ET1, EX1, ET0, EX0), IP B8H, TCON 88H, TMOD 89H, TL0 8AH, TL1 8BH, TH0 8CH, TH1 8DH, SCON 98H, SBUF 99H, PCON 87H.

Bit-addressable SFRs end with 0/8H. Usage: SETB TR1, JB TF0, MOV A,P0 etc. Controls all peripherals.

External Interrupt Signals in 8051

• \overline{INT0} (P3.2) & \overline{INT1} (P3.3): Active-low inputs. Trigger mode selectable via IT0/IT1 in TCON: ITx=0 level-triggered (low holds interrupt), ITx=1 edge-triggered (falling edge). Flags IE0/IE1 set; auto-cleared for edge after ISR.
• Vector addresses: INT0=0003H, INT1=0013H.
• Enable: EX0/EX1 in IE, global EA.
• Priority: PX0/PX1 in IP.
• Usage: Connect external device with pull-up, drive low pulse >1 machine cycle for edge; hold low until serviced for level.

Also serial and timer interrupts are internal but often listed.

Pin Diagram of 8051 – Utility

DIP-40: Pin 40 VCC (+5V), 20 GND, 18-19 XTAL2/XTAL1 (crystal), 9 RST (reset), 29 \overline{PSEN} (ext program enable), 30 ALE/\overline{PROG}, 31 \overline{EA}/VPP, 10-17 P3.0-7, 1-8 P1.0-7, 21-28 P2.0-7, 32-39 P0.0-7.

Utility:

• P0: AD0-7 multiplexed, needs latch.
• P2: A8-15.
• P3 alternates: RxD/TxD/INT0/INT1/T0/T1/WR/RD.
• Control: ALE latches address, PSEN reads ext ROM, EA selects int/ext program, RST reset high.
• Power/clock: VCC, GND, XTAL for oscillator.

Diagram description: rectangle with pins labelled clockwise; textual suffices.

Operation: With \overline{EA}=1 internal ROM used up to 4K then external; \overline{EA}=0 all external.

Memory Organization in 8051

Separate Harvard spaces: Program (64K, \overline{PSEN}) and Data (64K, \overline{RD}/\overline{WR}), plus Internal Data.

Internal Data (256B):

• 00H-1FH: 4 register banks (R0-R7) selectable by RS1,RS0 in PSW.
• 20H-2FH: 16 bytes bit-addressable (128 bits).
• 30H-7FH: General purpose RAM.
• 80H-FFH: SFRs (only direct addressing; 80H,88H...F0H bit-addressable).

External: Up to 64K program ROM (via \overline{PSEN}+ALE latch) and 64K data RAM (MOVX). \overline{EA}=0 forces external program from 0000H; =1 uses internal 0000-0FFFH then external beyond.

Access: MOV for internal direct/indirect, MOVX for external data, MOVC for program table.

Functions of SP and PC

Stack Pointer (SP, 81H, 8-bit): Points to top of stack in internal RAM. PUSH increments then writes, POP reads then decrements. SP=07H after reset → first push to 08H. Manages calls, interrupts, context save. Can relocate: MOV SP,#60H.

Program Counter (PC, 16-bit): Holds address of next instruction byte. Automatically increments on fetch; loaded by LJMP/AJMP/SJMP/CALL/RET/interrupt vectoring. Determines execution flow. Invisible directly but accessed via MOVC, PUSH PC via CALL.

Together they control sequence (PC) and LIFO storage (SP) for subroutines/interrupts.

SFRs for Interrupts, I/O, Timers

• Interrupts: IE A8H (enable: EA,ES,ET1,EX1,ET0,EX0), IP B8H (priority: PS,PT1,PX1,PT0,PX0), TCON 88H (flags IE1/IE0, IT1/IT0, TF1/TR1,TF0/TR0), SCON 98H (TI/RI for serial interrupt).
• I/O Ports: P0 80H, P1 90H, P2 A0H, P3 B0H – latches + alternate control via SCON/TCON.
• Timers/Counters: TMOD 89H (mode/GATE/C/T/M1M0 for both), TCON 88H (TF/TR/IE/IT), TH0/TL0 8CH/8AH, TH1/TL1 8DH/8BH, PCON 87H (T2 extra in 8052: T2CON etc.).

Set via MOV IE,#... ; MOV TMOD,#... ; MOV P1,#... etc.

General Purpose Registers & Flags/PSW in 8051

GPRs: Registers R0-R7 in 4 banks (00-07H,08-0FH,10-17H,18-1FH) selectable by RS1,RS0 (PSW.4-3). Plus Accumulator A, B, DPTR.

PSW (D0H) flags: CY (PSW.7) carry/borrow, AC (PSW.6) auxiliary carry for BCD, FO (PSW.5) user flag, RS1/RS0 (bank select), OV (PSW.2) signed overflow, P (PSW.0) parity (1 if odd parity in A).

SFRs: 21 SFRs as Q117. Categories: Ports, Timer (TMOD/TCON/THx/TLx), Serial (SCON/SBUF), Interrupt (IE/IP), Power (PCON), Control (PSW,SP,DPTR,ACC,B). Status register = PSW + SFRs.

Oscillator Circuit & Timing – see Q121

Crystal between XTAL1/2 with internal inverter, 30pF caps. Generates Fosc, divided by 12 for machine cycle (6 states ×2). ALE 1/6 Fosc, PSEN, timers, baud derived. 12MHz →1µs MC; 11.0592MHz →1.085µs ideal for baud. Reset needs 2 cycles high.

Functions of ALE, \overline{PSEN}, \overline{EA}, RST

• ALE (30): Address Latch Enable – active-high pulse at 1/6 Fosc to latch low address A0-A7 from P0 into external latch (74LS373). Demultiplexes address/data. Also used as \overline{PROG} for Flash programming.
• \overline{PSEN} (29): Program Store Enable – active-low output, reads external program memory (ROM) when CPU fetches outside internal. Connects to OE of external EPROM/Flash. Inactive high when executing internal.
• \overline{EA}/VPP (31): External Access – input. EA=1 → fetch internal first (0000-0FFFH) then external after; EA=0 → all fetches external, 0H vectors external. Also VPP 21V for EPROM programming.
• RST (9): Reset – active-high input, hold >2 machine cycles (>1µs) to reset PC=0000H, SP=07H, ports high, etc. Needs RC (10µF+8.2k) power-on.

Internal Memory Organization – see Q96

128B RAM: 00-1FH 4 banks, 20-2FH bit-addressable 16B, 30-7FH general, 80-FFH SFRs. 4KB ROM 0000-0FFFH internal program, beyond external via PSEN. Harvard separate data 64K via MOVX.

Memory Banks & Internal RAM Structure (8051)

Register Banks: 4 banks × 8 registers R0-R7 mapped 00-1FH: Bank0 00-07H, Bank1 08-0FH, Bank2 10-17H, Bank3 18-1FH. Selected by RS1 RS0 (PSW.4-3). Fast context switch for interrupts without PUSH.

Internal RAM 128B (00-7FH) or 256B (8052 00-FFH):

• 00-1FH banks (32B)
• 20-2FH bit-addressable 16B (128 bits, bit addr 00-7FH) for flags/semaphores.
• 30-7FH general scratch.
• 80-FFH SFRs (separate space, direct address only). In 8052, 80-FFH upper RAM accessible via indirect (@R0) vs SFR via direct.

Stack typically relocated to 30H+ to avoid bank collision; SP=07H default shares with bank1.

Alternate Functions of Port 0, Port 2, Port 3

• Port 0 (AD0-AD7): Normal quasi-I/O with pull-ups, but when external memory accessed, becomes multiplexed low address/data bus latched by ALE. Open-drain, needs external pull-up for input.
• Port 2 (A8-A15): Quasi I/O; alternately high address byte for external memory (stable during data phase). Does not need latch.
• Port 3 (8 alternates as Q1): P3.0 RxD, P3.1 TxD, P3.2 INT0, P3.3 INT1, P3.4 T0, P3.5 T1, P3.6 WR\ (data write strobe), P3.7 RD\ (data read). Selected when corresponding SFR bit enables function; else acts as I/O.

Bit vs Byte Addressing in 8051

• Byte addressing: Access entire 8-bit byte via direct or indirect address (00-7FH RAM, 80-FFH SFRs, etc.) e.g., MOV A,30H loads 8 bits; address granularity is byte.
• Bit addressing: Access single bit individually via bit address. 8051 has 211 bit addresses: 128 in RAM 20H-2FH (bits 00H-7FH where bit address = byte_address_offset×8 + bit) and 87 in SFRs ending 0/8H (e.g., PSW.7=CY, P1.0). Instructions: SETB bit, CLR bit, MOV C,bit, JB bit,rel. Bit address distinguishes via 8-bit bit address encoding vs byte direct. Example SETB 00H sets RAM 20H.0, SETB P1.0 vs MOV P1,#01H byte.

PSW Flags & SFR Types

PSW flags (D0H, bit-addressable): CY (7) carry, AC (6) aux carry, F0(5) user, RS1(4) RS0(3) bank select, OV(2) overflow, - (1) reserved, P(0) parity. Flags updated by arithmetic/logic: ADD affects CY,AC,OV,P etc.

SFR Types:

• Port SFRs: P0,P1,P2,P3
• Timer SFRs: TMOD,TCON,TH0,TL0,TH1,TL1
• Serial SFRs: SCON,SBUF,PCON
• Interrupt SFRs: IE,IP
• Control SFRs: PSW,SP,ACC,B,DPL,DPH
• Power/Misc: PCON

21 core SFRs in 80-FFH, accessed by direct addressing only, 11 bit-addressable. Control whole MCU.

Carry (CY) vs Overflow (OV) – Difference with Example

• CY (PSW.7): Unsigned overflow – carry out of bit7. 1 if result exceeds 255 (addition) or borrow in subtraction. For unsigned numbers.
• OV (PSW.2): Signed overflow – carry into sign bit XOR carry out. 1 if signed result exceeds -128..127. For signed 2's complement.

Example:

1. MOV A,#0FFH; ADD A,#01H → A=00H, CY=1 (unsigned overflow 255+1), AC=1, OV=0 (signed -1+1=0 no overflow). CY indicates unsigned wrap.
2. MOV A,#7FH; ADD A,#01H → A=80H, CY=0 (no unsigned overflow), OV=1 (signed 127+1 = -128 overflow). This shows signed overflow without carry.

Check: OV = CY6 XOR CY7.

SFRs Associated with I/O Ports & Input Configuration

• Port Latches: P0 (80H), P1 (90H), P2 (A0H), P3 (B0H) – each bit latch + driver with pull-up (P0 open-drain).

Input Configuration: 8051 ports are quasi-bidirectional. To configure pin as input:

1. Write 1 to latch: MOV P1,#0FFH or SETB P1.3 makes FET off, pull-up holds high, external can drive low/high.
2. Read pin: MOV A,P1 reads pin state (not latch). If alternative function enabled, direction auto.

Example:

MOV P1,#0FFH ; P1 input
MOV A,P1 ; read
ANL A,#01H
JNZ NOT_PRESSED

Alternative functions selected via SFR controls (SCon, TCon etc.) override I/O.

SFRs Associated with Interrupt Module (as Q46/118)

IE A8H (enable bits EA,ES,ET1,EX1,ET0,EX0), IP B8H (priority PS,PT1,PX1,PT0,PX0), TCON 88H (IE1/IT1,IE0/IT0,TF1/TR1,TF0/TR0), SCON 98H (TI/RI). For 8052, additional T2CON etc. Vectors at 0003H-0023H.

Short Notes: Interrupts (8051)

• Sources 5 (INT0, T0, INT1, T1, Serial), vectors 0003-0023H, priority fixed via hardware polling but overridden by IP.
• Enable via IE (EA global), request flags in TCON/SCON, trigger modes via ITx.
• Response: finish instruction →push PC→vector →ISR→RETI pops.
• Latency 3-8 cycles, nested allowed.
• Applications: external events, timing, communication.

Short Notes: I/O Ports – see Q119/21

4×8-bit ports P0-P3 quasi-bidirectional, P0 AD multiplexed, P2 high address, P3 alternates (RxD/TxD/INT/Timer/WR/RD), P1 pure I/O. Write 1 for input. Each port SFR latch+driver.

Address, Data, Control Bus in 8051

• Address Bus (16-bit, unidirectional): A15-A8 via P2 (high) stable, A7-A0 via P0 multiplexed→latch. Selects 64K program/data.
• Data Bus (8-bit, bidirectional): D7-D0 via P0 after ALE, carries data CPU↔memory/peripherals. Shared with address time-multiplexed.
• Control Bus: ALE (latch), \overline{PSEN} (program read), \overline{RD}/\overline{WR} (P3.7/6 data read/write), \overline{EA}, RST, INTx. Generated by timing & control unit from clock. Manage direction and timing.

Short Notes: Stack & Stack Pointer

• Stack: LIFO area in internal RAM (default 08H upward), holds return addresses, register context, data via PUSH/POP.
• SP (81H): Points to top. Reset 07H. PUSH → SP++ then store; POP → load then SP--. Relocate: MOV SP,#60H to avoid overlap with register banks/bit area. Depth limited by RAM (max 128-7FH). Overflow collides SFRs.