Central Processing Unit (CPU) organization and working

Central Processing Unit (CPU) organization and working

1. What the CPU Does

The CPU executes the instructions held in main memory. It performs four jobs repeatedly: fetch the instruction, decode it, execute it and store the result. Everything a computer does — a click, a keystroke, a print job — is ultimately a sequence of these machine instructions.

2. Three Major Parts of the CPU

Part	Nature	Job
ALU (Arithmetic Logic Unit)	Combinational circuit	Arithmetic ($+, -, ×, ÷$, increment) and logic (AND, OR, NOT, XOR, compare, shift) operations; sets status flags
Control Unit (CU)	Sequential circuit	Fetches and decodes instructions, generates control/timing signals, synchronises every unit with the clock
Register set	Fastest storage inside CPU	Holds operands, addresses, the instruction itself and intermediate results

3. Register Organisation

Register	Full form	Function
PC	Program Counter	Holds address of the next instruction; auto-increments
IR	Instruction Register	Holds the current instruction while it is decoded
MAR	Memory Address Register	Address sent to memory on the address bus
MBR (MDR)	Memory Buffer/Data Register	Data coming from / going to memory
AC	Accumulator	Default operand and result register of the ALU
SP	Stack Pointer	Top of the runtime stack (function calls, return addresses)
FLAGS / PSW	Program Status Word	Carry, Zero, Sign, Overflow, Parity, Interrupt-enable bits
GPRs	General Purpose Registers	R0-R15 etc. for operands and fast temporary storage
IX / Index regs	Index Registers	Address computation for arrays and loops

4. Instruction Cycle (Machine Cycle)

        ┌──────────────────────── FETCH ────────────────────────┐
        │  MAR ← PC ;  read memory ;  MBR → IR ;  PC ← PC + 1   │
        └───────────────────────────┬───────────────────────────┘
                                    ▼
        ┌────────────────────── DECODE ────────────────────────┐
        │  CU decodes opcode, identifies operands & addressing  │
        └───────────────────────────┬────────────────────────┘
                                    ▼
        ┌────────────────────── EXECUTE ───────────────────────┐
        │  ALU computes  /  memory read-write  /  I-O transfer  │
        └───────────────────────────┬────────────────────────┘
                                    ▼
        ┌────────────────────── STORE ─────────────────────────┐
        │  result written to register/memory, flags updated     │
        └──────────────────────────────────────────────────────┘

If the operand is in memory, an extra memory read cycle is inserted inside EXECUTE.

5. Clock, CPI and Performance

The CPU is driven by a quartz clock of frequency $f$; one clock period is

The time to run a program of $I$ instructions with average $CPI$ clock cycles per instruction is

Throughput in millions of instructions per second:

Numerical example: $f$ = 2 GHz, $CPI$ = 2.5, $I = 10^{9}$ instructions →
$T_{ck} = 0.5$ ns, $Exec = 10^{9} × 2.5 × 0.5$ ns = 1.25 s, and $MIPS = 2×10^{9} / (2.5 × 10^{6}) = 800$ MIPS.

6. Pipelining

Instead of finishing one instruction before starting the next, a pipeline overlaps stages — while instruction 1 executes, instruction 2 decodes and instruction 3 is fetched. For $k$ stages and $n$ instructions:

(for large $n$, $S → k$). Hazards that spoil this: structural (resource clash), data (dependency), control (branch — handled by branch prediction).

7. RISC vs CISC

Feature	RISC	CISC
Instruction set	Small, simple, fixed length	Large, complex, variable length
Cycles per instruction	~1	Many
Addressing modes	Few	Many
Registers	Many	Fewer
Control	Hardwired	Micro-programmed
Pipelining	Easy and efficient	Difficult
Examples	ARM, MIPS, RISC-V, SPARC	Intel x86, AMD, VAX

8. Exam Points

• Draw the internal organisation of the CPU and explain ALU, CU and registers — 7 marks, frequent.
• Explain the instruction cycle with a flow diagram — 5 marks.
• Difference between RISC and CISC — 5 marks, very frequent.
• Numerical on execution time / MIPS / clock period — 3-5 marks.
• Draw and explain the register set (PC, IR, MAR, MBR, AC, SP, flags) — 5 marks.
• What is pipelining? Derive the speed-up — 5 marks.